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Paper List of FPL from 1991 to 2014

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  • eecejk
    We provide the FPL paper list from 1991 to 2014. You can also refer to the attached excel file to have access to paper IDs. Notice that a paper ID is shown at
    Message 1 of 26 , Feb 9, 2015

      We provide the FPL paper list from 1991 to 2014. You can also refer to the attached excel file to have access to paper IDs. 

      Notice that a paper ID is shown at the most left place : e.g., 91-1 (published year - number). 

    • eecejk
      1991 Paper List 91-1 Paul Chow A 1.2um CMOS FPGA using cascaded logic blocks and segmented routing 91-2 John F. McDonald A fine grained, highly fault tolerant
      Message 2 of 26 , Feb 9, 2015

        1991 Paper List


        Paul Chow

         A 1.2um CMOS FPGA using cascaded logic blocks and segmented routing


        John F. McDonald

        A fine grained, highly fault tolerant system based on WSI and FPGA technology


        Reiner W. Hartenstein

        A novel compilation technique for a machine paradigm based on field-programmable logic


        Kenneth Chan

        A PC-based oscilloscope system incorporating a xilinx logic cell array


        Jon Stewart

        A petri net-based framestore


        Alvise Sartori

        A smart camera


        Nam-Sung Woo

        A study on the structure of the intermediate network in an FPGA technology mapping


        David Hawley

        Advanced PLD architectures


        Stephen Trimberger

        Beyond logic - FPGAs for digital systems


        Colin Carruthers

        Bipolar CAL chip doubles speed of FPGAs


        Ian Page

        Compiling occam into FPGAs


        Bradley Felton

        Configuration data verification and the integrity checking of SRAM-based FPGAs


        Patrick Lysaght

        Dynamically reconfigurable logic in undergraduate projects


        Martine Schlag

        Empirical evaluation of multilevel logic minimization tools for an FPGA technology


        Ulrich Weinmann

        Evaluation of FPGA architectures


        Turo Piila

        Experiences on fast ASIC prototyping using altera circuits


        Martin Colley

        Experiences using reprogrammable logic devices within undergraduate courses


        Jouni Isoaho

        High resolution DAC design based on FPGAs


        Omero Bigalli

        HPGI: A hardware progammable generic interface for the IBM PC


        Erik Brunvand

        Implementing self-timed systems with FPGAs


        John Oldfield

        Implementing self-timed systems: Comparison of configurable logic arrays with full-custom circuits


        Glenn Rosendahl

        In-system reprogrammable LCAs provide a versatile interface for a DSP-based parallel machine


        Beat Heeb

        Logic minimization for novel programmable logic architectures


        Frank Dresigand

        Logic synthesis for universal logic cells


        Masahiro Fujita

        Minimization of look-up table FPGAs based on minimal support


        Franco Pirri 

        P-net user interface


        Marian Adamski

        Parallel controller implementation using standard PLD software


        Wayne Luk

        Parameterising designs for FPGAs


        Richard C. Seals

        Partitioning a design into several PLDs: a video digitiser


        Jean-Michel Vuillanzy

        Performance evaluation and enhancement of FPGAs


        Warren East 

        Practical fpga design using logic synthesis


        Jesse Jenkins

        Programmable macro logic - the pml 2852


        Oliver Rettig

        Prototyping of a wheel slip evaluating circuit with FPGAs


        John F. Beetem

        Simultaneous placement and routing of the LABYRINTH reconfigurable logic array


        Matthias Groh

        Technology mapping for look-up table FPGAs


        Dwight Hill

        The benefits of flexibility in look-up table FPGAs


        Cuno Pfister

        The LABRYS project


        Carl Ebeling

        TRIPTYCH: a new FPGA architecture


        Demessie Girma

        Undergraduate training in ASIC design techniques


        Sean Monaghan

        Use of FPGAs in computational physics


        Ifor Williams

        Using FPGAs to prototype new computer architectures


        Kevin Chung

        Using hierarchical logic blocks to improve the speed of FPGAs


        David C. Blight

        VHDL for FPGA design

      • eecejk
        92-1 Paul Shaw A highly parallel FPGA-based machine and its formal verification 92-2 Lennart Lindh A real-time kernel - rapid prototyping with VHDL and FPGAs
        Message 3 of 26 , Feb 9, 2015
          92-1Paul ShawA highly parallel FPGA-based machine and its formal verification
          92-2Lennart LindhA real-time kernel - rapid prototyping with VHDL and FPGAs
          92-3Dave AllenAutomatic one-hot re-encoding for FPGAs.
          92-4Beat HeebChameleon: A workstation of a different colour
          92-5Georg KempaFPGA based logic synthesis of squarers using VHDL
          92-6Arno KunzmannFPGA based self-test with deterministic test patterns
          92-7Dzung T. HoangFPGA implementation of systolic sequence alignment
          92-8Peter PoechmuellerHigh level synthesis in an FPGA-based computer aided prototyping environment
          92-9Herbert GrünbacherJAPROC - an 8-bit micro controller design and its test environment
          92-10Li-Fei WuMinimization of permuted reed-muller trees for cellular logic programmable gate arrays
          92-11Scott HauckMONTAGE: An FPGA for synchronous and asynchronous circuits
          92-12Naohisa OhtaNew application of FPGAs to programmable digital communication circuits
          92-13Andreas AstNovel high performance machine paradigms and fast-turnaround ASIC design methods
          92-14Hartmut SurmannOptimized fuzzy controller architecture for field programmable gate arrays
          92-15Dwight HillORCA: A new architecture for high-performance FPGAs
          92-16Günter BiehlOverview of Complex Array-Based PLDs
          92-17Masahiro FujitaPatching method for lookup-table type FPGAs
          92-18David C. BlightSelf-organizing kohonen maps for FPGA placement
          92-19Alberto Sangiovanni-VincentelliSome considerations on field-programmable gate arrays and their impact on system design
          92-20Bradly K. FawcettSRAM-based FPGAs ease system verification
          92-21Jouni IsoahoTechnologies and uilisation of field-programmable gate arrays
          92-22Arne LindeUsing FPGAs to implement a reconfigurable highly parallel computer
          92-23Eric BrunvandUsing FPGAs to prototype a self-timed computer
        • eecejk
          1993 paper list 93-1 Josef Mayrhofer A control circuit for electrical drives based on transputers and FPGAs 93-2 Hiroshi Nakada A design method for realising
          Message 4 of 26 , Feb 9, 2015
            1993 paper list

            93-1Josef MayrhoferA control circuit for electrical drives based on transputers and FPGAs
            93-2Hiroshi NakadaA design method for realising real-time circuits on mulfiple-FPGA systems
            93-3Paul DugganA field-programmable multi-chip module for implementing boolean neural networks
            93-4Joachim KönigA high-speed FPGA-based interface to high-bandwidth hardware
            93-5Steven A. GuccioneA neural network implementation using reconfigurable architectures
            93-6Narasimha B. BhatA new library-based mapper for LUT FPGAs
            93-7Tobias BlickleA prototyping array for parallel architectures
            93-8Andreas KochA universal co-processor for workstations
            93-9Kam W. NgA writeable instruction set co-processor using FPGAs
            93-10Qiang WangAn array architecture for reconfigurable datapaths
            93-11David RossAn FPGA-based hardware accelerator for image processing
            93-12Bradly K. FawcettApplications of reconfigurable logic
            93-13Marleen AdéCommunication primitives on FPGAs in a heterogeneous multi-processor emulation environment
            93-14Dietmar LoyCorrelative ultrasonic distance measurement system
            93-15M. F. DossisCustom co-processor compilation
            93-16Barry FaginDartMIPS: a case study in quantitative analysis of processor design tradeoffs using FPGAs
            93-17Andy CarpenterDetermining optimal architectures for configurable devices
            93-18Patrick LysaghtDynamic reconfiguration of FPGAs
            93-19Runip GopisettyExploration of multiplexer-based FPGA logic modules
            93-20Eduardo BoemoField-programmable logic in education: a case study
            93-21Neil HowardFPGA acceleration of electronic design automation tasks
            93-22Ulrich WeinmannFPGA partitioning under timing constraints
            93-23Mohamed WahabFPGA-based DSP systems
            93-24Henry L. OwenFPGA-based emulator architectures
            93-25Jouni IsoahoFPGA-implementable digital filters
            93-26Christopher KapplerGenetic string distance evaluation with an array of self-timed FPGA chips
            93-27Sean MonaghanHigh-level hardware synthesis for large scale computational physics targetted at FPGAs
            93-28Kai Wing TseImplementation of pre-processing and feature extraction of chinese characters with FPGAs
            93-29Kai Wing TseImplementation of the data encryption standard algorithm with FPGAs
            93-30Miriam LeeserImplementing filters with programmable logic
            93-31Malkit S. JhittaIntroduction of a new FPGA architecture
            93-32Alesssandro BelliniModular statecharts for designing parallel controllers
            93-33Ian PageParameterised processor generation
            93-34Richard G. ShoupParameterized convolution filtering in an FPGA
            93-35Tudor JebeleanRational arithmetic using FPGAs
            93-36Patrick FoulkReconfigurable computing with SRAM programmable gate arrays
            93-37John HurdleReliable interfacing of self-timed FPGA-based neural classifiers to synchronous parts
            93-38Javier MoránSigned digit arithmetic on FPGAs
            93-39Jon FrankleSpecifying and accomimoditing FPGA timing requirements
            93-40Wayne LukStructured hardware compilation of parallel programs
            93-41Maureen PearceSynthesis strategies for concurrent logic FPGAs
            93-42Endric SchubertThe use of FPGAs for educational purposes in VLSI microprocessor design
            93-43Srilata RamanTiming-based placement for an FPGA design environment
            93-44Jeffrey M. ArnoldVHDL progamming on splash 2
            93-45Erik BrunvandWindchime: an FPGA-based self-timed parallel processor

          • eecejk
            1994 paper list 94-1 John Ant. Hallas A CAD tool for development of an extra-fast fuzzy logic controller based on FPGAs and memory modules 94-2 Gerd von Bögel
            Message 5 of 26 , Feb 9, 2015
              1994 paper list

              94-1John Ant. HallasA CAD tool for development of an extra-fast fuzzy logic controller based on FPGAs and memory modules
              94-2Gerd von BögelA design environment with emulation of prototypes for hardware/software systems using Xilinx FPGA
              94-3Valentina SalapuraA fast FPGA implementation of a general purpose neuron
              94-4Ibrahim bin MatA FPL prototyping package with a C++ interface for the PC bus
              94-5Ismail HaritaogluA global routing heuristic for FPGAs based on mean field annealing
              94-6Om P. AgrawalA high density complex PLD family optimized for flexibility, predictability and 100% routability
              94-7Jan LichtermannA high-speed rotation processor
              94-8J. C. DebizeA job dispatcher-collector made of FPGAs for a centralized voice server
              94-9Stephan GehringA laboratory for a digital design course using FPGAs
              94-10Reiner W. HartensteinA new FPGA architecture for word-oriented datapaths
              94-11Barry FaginA reprogrammable processor for fractal image compression
              94-12Toshiaki MiyazakiA speed-up technique for synchronous circuits realized as LUT-based FPGAs
              94-13Christian IseliA superscalar and reconfigurable processor
              94-14Ricardo de O. DuranteA test methodology applied to cellular logic programmable gate arrays
              94-15Volker HamannA testbench design method suitable for FPGA-based prototyping of reactive systems
              94-16André KlindworthA tool-set for simulating Altera-PLDs using VHDL
              94-17A. R. NaseerAn efficient technique for mapping RTL structures onto FPGAs
              94-18J. DepreitereAn optoelectronic 3-D field programmable gate array
              94-19P. LysaghtArtificial neural network implementation on a fine-grained FPGA
              94-20Mat NewmanConstraint-based heirarchical placement of parallel programs
              94-21Nigel ToonContinuous interconnect provides solution to density/performance trade-off in programmable logic
              94-22U. Meyer-BäseCOordinate Rotation DIgital Computer (CORDIC) synthesis for FPGA
              94-23A. AstData-procedural languages for FPL-based machines
              94-24P. LysaghtDesign experience with fine-grained FPGAs
              94-25Juan J. Rodríguez-AndinaDesign of safety systems using field programmable gate arrays
              94-26T. SaluvereDirect sequence spread spectrum digital radio DSP prototyping using Xilinx FPGAs
              94-27Jouni IsoahoDSP development fith full-speed prototyping based on HW/SW codesign techniques
              94-28David LamEducational use of field programmable gate arrays
              94-29Gerhard R. CadekExperiences using XBLOX for implementing a digital filter algorithm
              94-30Michael HermannFault modeling and test generation for FPGAs
              94-31R. B. HughesFormal CAD techniques for safety-critical FPGA design and deployment in embedded subsystems
              94-32Tibor BartosFormal verification of timing rules in design specifications
              94-33Apostolos DollasFPGA based low cost generic reusable module for the rapid prototyping of subsystems
              94-34Th. BennerFPGA based prototyping for verification and evaluation in hardware-software cosynthesis
              94-35R. NguyenFPGA based reconfigurable architecture for a compact vision system
              94-36Bradley K. FawcettFPGA development tools: Keeping pace with design complexity
              94-37Andrew LeaverFPGA routing structures for real circuits
              94-38Amir H. FarrahiFPGA technology mapping for power minimization
              94-39Bradly K. FawcettHardWire: A risk-free FPGA-to-ASIC migration path
              94-40Tsuyoshi IsshikiHigh-performance datapath implementation on field-programmable multi-chip module (FPMCM)
              94-41Peter M. AthanasImage processing on a custom computing platform
              94-42Mohamed AkilImplementation and performance evaluation of an image pre-processing chain on an FPGA
              94-43Tudor JebeleanImplementing GCD systolic arrays on FPGA
              94-44Marc DumasImplementing on line arithmetic on PAM
              94-45M. RobertsInfluence of logic block layout architecture on FPGA performance
              94-46Michal Z. ServítIntegrated layout synthesis for FPGAs
              94-47Georg J. KempaMARC: A Macintosh NUBUS-expansion board based reconfigurable test system for validating communication systems
              94-48Steven H. KelemMeaningful benchmarks for logic optimization of table-lookup FPGAs
              94-49Kaushik RoyOn channel architecture and routability for FPGAs under faulty conditions
              94-50Attila KatonaOn some limits of Xilinx based control logic implementations
              94-51Andrzej HlawiczkaOptimized synthesis of self-testable finite state machines (FSM) using BIST-PST structures in Altera structures
              94-52C. P. CowenPerformance characteristics of the monte-carlo clustering processor (MCCP) -- a field programmable logic based custom computing machine
              94-53Kaushik RoyPower dissipation driven FPGA place and route under delay constraints
              94-54Nigel ToonReconfigurable hardware from programmable logic devices
              94-55E. P. KaloshaSignature testability of PLA
              94-56Richard W. WielerSimulating static and dynamic faults in BIST structures with a FPGA based emulator
              94-57Xiao yu ChenSoftware environment for WASMII: a data driven machine with a virtual hardware
              94-58Hans-Huergen BrandSpecification and synthesis of complex arithmetic operators for FPGAs
              94-59Jirí DanecekThe architecture of a general-purpose processor cell
              94-60Michael GschwindThe design of a stack-based microprocessor
              94-61P. GramataThe MD5 message-digest algorithm in the Xilinx FPGA
              94-62Eugene GoldbergUsing consensusless covers for fast operating on boolean functions
              94-63Tormod NjølstadZAREPTA: A zero lead-time, all reconfigurable system for emulation, prototyping and testing of ASICs

            • eecejk
              1995 paper list 95-1 Paul Dunn A configurable logic processor for machine vision 95-2 Paul Graham A hardware genetic algorithm for the travelling salesman
              Message 6 of 26 , Feb 9, 2015
                1995 paper list

                95-1Paul DunnA configurable logic processor for machine vision
                95-2Paul GrahamA hardware genetic algorithm for the travelling salesman problem on SPLASH 2
                95-3D. R. WoodwardA programmable I/O system for real-time AC drive control applications
                95-4M. AtiaA self-validating temperature sensor implemented in FPGAs
                95-5Michael GschwindA VHDL design methodolgy for FPGAs
                95-6U. ZahmAdvanced method for industry related education with an FPGA design self-learning kit
                95-7Russell J. PetersenAn assessment of the suitability of FPGA-based systems for use in digital signal processing
                95-8Keith DimondAn automatic technique for realising user interaction processing in PLD based systems
                95-9Peter LeeAn FPGA prototype for a multiplierless FIR filter built using the logarithmic number system
                95-10Maya GokhaleAutomatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays
                95-11L. E. TurnerBIT-serial FIR filters with CSD coefficients for FPGAs
                95-12Steven A. GuccioneClassification and performance of reconfigurable architectures
                95-13W. P. MarnaneCompiling regular arrays onto FPGAs
                95-14Shaori GuoCompiling Ruby into FPGAs
                95-15Steve CasselmanCreation of hardware objects in a reconfigurable computer
                95-16Fabio GuerreroCustomised hardware based on the REDOC III algorithm for high-performance date ciphering
                95-17A. R. NaseerDelay minimal mapping of RTL structures onto LUT based FPGAs
                95-18Alan WenbanDeveloping interface libraries for reconfigurable data acquisition boards
                95-19Peter SchulzExtending DSP-boards wih FPGA-based structures of interconnection
                95-20Tudor JebeleanFPGA implementation of a rational adder
                95-21André KlindworthFPLD implementation of computation over finite fields GF(2 verb +^+m) with applications to error control coding
                95-22Ramana V. RachakondaHigh-speed region detection and labeling using an FPGA based custom computing platform
                95-23Brad L. HutchingsImplementation approaches for reconfigurable logic applications
                95-24Nabeel ShiraziImplementation of a 2-D fast fourier transform on an FPGA-based custom computing machine
                95-25G. PanneerselvamImplementation of fast fourier transforms and discrete cosine transforms in FPGAs
                95-26Markus WeinhardtInteger programming for partitioning in software oriented codesign
                95-27J. TurnerMigraton of a dual granularity globally interconnected PLD architecture to a 0.5 um TLM process
                95-28Massimiliano CorbaModular architecture for real-time astronomical image processing with FPGAs
                95-29H. -J. HerpelPrototype generation of application-specific emedded controllers for microsystems
                95-30Patrick LysaghtPrototyping environment for dynamically reconfigurable logic
                95-31L. E. TurnerRapid hardware prototyping of digital signal processing systems using FPGAs
                95-32Rajani CuddapahReconfigurable logic for fault-tolerance
                95-33Rob PayneSelf-timed FPGA systems
                95-34Eduardo I. BoemoSome notes on power management on FPGA-based systems
                95-35Steven A. GuccioneSupercomputing with reconfigurable architectures
                95-36Toshiaki MiyazakiTelecommunication-oriented FPGA and dedicated CAD system
                95-37Kristin AhrensTest standard serves dual role as on-board programming solution
                95-38David GreavesThe CSYN verilog compiler and other tools
                95-39Anthony StansfieldThe design of a new FPGA architecture
                95-40Carol A. FieldsThe proper use of hierarchy in HDL-based high density FPGA design
                95-41Greg SniderThe teramac configurable computer engine
                95-42Gordon BrebnerUse of reconfigurability in variable-length code detection at video rates
                95-43Cristophe BeaumontUsing FPGAs as control support in MIMD executions
                95-44Adrian LawrenceUsing reconfigurable hardware to speed up product development and performance
                95-45Maziar KhosravipourVHDL-based rapid hardware prototyping using FPGA technology
                95-46Steven ChurcherXC6200 fastmap(tm) processor interface

              • eecejk
                1995 paper list 95-1 Paul Dunn A configurable logic processor for machine vision 95-2 Paul Graham A hardware genetic algorithm for the travelling salesman
                Message 7 of 26 , Feb 9, 2015
                  1995 paper list

                  95-1Paul DunnA configurable logic processor for machine vision
                  95-2Paul GrahamA hardware genetic algorithm for the travelling salesman problem on SPLASH 2
                  95-3D. R. WoodwardA programmable I/O system for real-time AC drive control applications
                  95-4M. AtiaA self-validating temperature sensor implemented in FPGAs
                  95-5Michael GschwindA VHDL design methodolgy for FPGAs
                  95-6U. ZahmAdvanced method for industry related education with an FPGA design self-learning kit
                  95-7Russell J. PetersenAn assessment of the suitability of FPGA-based systems for use in digital signal processing
                  95-8Keith DimondAn automatic technique for realising user interaction processing in PLD based systems
                  95-9Peter LeeAn FPGA prototype for a multiplierless FIR filter built using the logarithmic number system
                  95-10Maya GokhaleAutomatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays
                  95-11L. E. TurnerBIT-serial FIR filters with CSD coefficients for FPGAs
                  95-12Steven A. GuccioneClassification and performance of reconfigurable architectures
                  95-13W. P. MarnaneCompiling regular arrays onto FPGAs
                  95-14Shaori GuoCompiling Ruby into FPGAs
                  95-15Steve CasselmanCreation of hardware objects in a reconfigurable computer
                  95-16Fabio GuerreroCustomised hardware based on the REDOC III algorithm for high-performance date ciphering
                  95-17A. R. NaseerDelay minimal mapping of RTL structures onto LUT based FPGAs
                  95-18Alan WenbanDeveloping interface libraries for reconfigurable data acquisition boards
                  95-19Peter SchulzExtending DSP-boards wih FPGA-based structures of interconnection
                  95-20Tudor JebeleanFPGA implementation of a rational adder
                  95-21André KlindworthFPLD implementation of computation over finite fields GF(2 verb +^+m) with applications to error control coding
                  95-22Ramana V. RachakondaHigh-speed region detection and labeling using an FPGA based custom computing platform
                  95-23Brad L. HutchingsImplementation approaches for reconfigurable logic applications
                  95-24Nabeel ShiraziImplementation of a 2-D fast fourier transform on an FPGA-based custom computing machine
                  95-25G. PanneerselvamImplementation of fast fourier transforms and discrete cosine transforms in FPGAs
                  95-26Markus WeinhardtInteger programming for partitioning in software oriented codesign
                  95-27J. TurnerMigraton of a dual granularity globally interconnected PLD architecture to a 0.5 um TLM process
                  95-28Massimiliano CorbaModular architecture for real-time astronomical image processing with FPGAs
                  95-29H. -J. HerpelPrototype generation of application-specific emedded controllers for microsystems
                  95-30Patrick LysaghtPrototyping environment for dynamically reconfigurable logic
                  95-31L. E. TurnerRapid hardware prototyping of digital signal processing systems using FPGAs
                  95-32Rajani CuddapahReconfigurable logic for fault-tolerance
                  95-33Rob PayneSelf-timed FPGA systems
                  95-34Eduardo I. BoemoSome notes on power management on FPGA-based systems
                  95-35Steven A. GuccioneSupercomputing with reconfigurable architectures
                  95-36Toshiaki MiyazakiTelecommunication-oriented FPGA and dedicated CAD system
                  95-37Kristin AhrensTest standard serves dual role as on-board programming solution
                  95-38David GreavesThe CSYN verilog compiler and other tools
                  95-39Anthony StansfieldThe design of a new FPGA architecture
                  95-40Carol A. FieldsThe proper use of hierarchy in HDL-based high density FPGA design
                  95-41Greg SniderThe teramac configurable computer engine
                  95-42Gordon BrebnerUse of reconfigurability in variable-length code detection at video rates
                  95-43Cristophe BeaumontUsing FPGAs as control support in MIMD executions
                  95-44Adrian LawrenceUsing reconfigurable hardware to speed up product development and performance
                  95-45Maziar KhosravipourVHDL-based rapid hardware prototyping using FPGA technology
                  95-46Steven ChurcherXC6200 fastmap(tm) processor interface

                • eecejk
                  1996 paper list 96-1 T. Kean A fast constant coefficient multiplier for the XC6200 96-2 W. Luk A framework for developing parametrised FPGA libraries 96-3 K.
                  Message 8 of 26 , Feb 9, 2015
                    1996 paper list

                    96-1T. KeanA fast constant coefficient multiplier for the XC6200
                    96-2W. LukA framework for developing parametrised FPGA libraries
                    96-3K. YiA new FPGA technology mapping approach by cluster merging
                    96-4N. JanzenA slow motion engine for the analysis of FPGA-based prototypes
                    96-5G. BrebnerA virtual hardware operating system for the Xilinx XC6200
                    96-6J. R. HaddyAn asynchronous transfer mode (ATM) stream demultiplexer and switch
                    96-7Y. ShibataAn emulation system of the WASMII: A data driven computer on a virtual hardware
                    96-8L. LarssonAn EPLD based transient recorder for simulation of video signal processing devices in a VHDL environment close to system level conditions
                    96-9A. TrostAn experimental programmable environment for prototyping digital circuits
                    96-10J. StohmannAn universal CLA adder generator for SRAM-based FPGAs
                    96-11I. P. HeronArchitectural strategies for implementing an image processing algorithm on XC6OOO FPGA
                    96-12D. W. TrainorArchitectural synthesis and efficient circuit implementation for field programmable gate arrays
                    96-13M. VasilkoArchitectural synthesis techniques for dynamically reconfigurable logic
                    96-14A. BalboniASIC design and FPGA design: A unified design methodology applied to different technologies
                    96-15K. InoueATTEMPT- 1: A reconfigurable multiprocessor testbed
                    96-16U. OberCAPpartx: Computer aided prototyping partitioning for Xilinx FPGAs
                    96-17Z. SalcicCCSimP - an instruction-level custom-configurable processor for FPLDs
                    96-18U. Meyer-BäseCoherent demodulation with FPGAs
                    96-19C. H. DickComputing 2-D DFTs using FPGAs
                    96-20M. WeinhardtComputing weight distributions of binary linear block codes on a CCM
                    96-21S. PillementConcurrent design of hardware/software dedicated systems
                    96-22U. Meyer-BäseConvolutional error decoding with FPGAs
                    96-23R. W. HartensteinCustom computing machines vs. hardware/software codesign: From a globalized point of view
                    96-24J. L. RuizDesign of a VME parametrized library for FPGAs
                    96-25G. SchumacherDevelopment of a telephone answering machine in a lab - FPGAs in education
                    96-26T. MiyazakiFACT: Co-evaluation environment for FPGA architecture and CAD system
                    96-27H. EggersFast reconfigurable crossbar switching in FPGAs
                    96-28C. H. DickFIR filtering with FPGAs using quadrature sigma-delta modulation encoding
                    96-29K. TammemäeFlexible codesign target architecture for early prototyping of CMIST systems
                    96-30V. TchoumatchenkoFPGA design migration: Some remarks
                    96-31C. SanzFPGA implementation of the block-matching algorithm for motion estimation in image coding
                    96-32G. YasarGrowable FPGA macro generator
                    96-33A. HesenerImplementing reconfigurable datapaths in FPGAs for adaptive filter design
                    96-34K. RowleyImplementing sigma delta modulator prototype designs on an FPGA
                    96-35A. DitzingerKey issues for user acceptance of FPGA design tools
                    96-36N. LesterLogic synthesis for FPGAs using a mixed exclusive- / inclusive- OR form
                    96-37B. M. RoginaMetastability characteristics testing for programmable logic design
                    96-38M. GschwindMigration from schematic-based designs to a VHDL synthesis environment
                    96-39M. VasilkoOptically reconfigurable FPGAs: Is this a future trend?
                    96-40M. BraunParallel CRC computation in FPGAs
                    96-41Legl C.Performance-directed technology mapping for LUT-based FPGAs - what role do decomposition and covering play?
                    96-42M. WeinhardPortable pipeline synthesis for FCCMs
                    96-43D. SmithRACE: Reconfigurable and adaptive computing environment
                    96-44C. EbelingRaPiD - reconfigurable pipelined datapath
                    96-45B. L. CombridgeReconfigurable DSP demonstrators for the development of spacecraft payload processors
                    96-46S. CasselmanReconfigurable logic based fibre channel network card with sub 2 micro-second raw latency
                    96-47T. SuyamaSolving satisfiability problems on FPGAs
                    96-48S. H-. M. LudwigThe design of a coprocessor board using Xilinx's XC6200 FPGA - an experience report
                    96-49A. TouhafiThe implementation of a field programmable logic based co-processor for the acceleration of discrete event simulators
                    96-50S. GehringThe trianus system and its application to custom computing

                  • eecejk
                    1997 paper list 97-1 Tom Kean A 800 Mpixel/sec reconfigurable image correlator on XC6216 97-2 Mark Shand A case study of algorithm implementation in
                    Message 9 of 26 , Feb 9, 2015
                      1997 paper list

                      97-1Tom KeanA 800 Mpixel/sec reconfigurable image correlator on XC6216
                      97-2Mark ShandA case study of algorithm implementation in reconfigurable hardware and software
                      97-3Jason LeonardA case study of partially evaluated hardware circuits: Key-specific DES
                      97-4Anton Velinov ChichkovA hardware/software partitioning algorithm for custom computing machines
                      97-5Thomas HollsteinA prototyping environment for fuzzy controllers
                      97-6Igor KostarnovA reconfigurable approach to low cost media processing
                      97-7Ferran LisaA reconfigurable coprocessor for a PCI-based real time computer vision system
                      97-8Anjit Sekhar ChaudhuriA reconfigurable data-localised array for morphological algorithms
                      97-9Kazumasa NukataA reconfigurable sensor-data processing system for personal robots
                      97-10T. MathewsAn FPGA implementation of a matched filter detector for spread spectrum communications systems
                      97-11Sayan TeerapanyawattAn NTSC and PAL closed caption processor
                      97-12Rainer KressAn operating system for custom computing machines based on the Xputer paradigm
                      97-13Tudor JebeleanAuto-configurable array for GCD computation
                      97-14Gordon BrebnerAutomatic identification of swappable logic units in XC6200 circuitry
                      97-15S. J. B. AcockAutomatic mapping of algorithms onto multiple FPGA-SRAM modules
                      97-16Toshiaki MiyazakiCAD-oriented FPGA annd dedicated CAD system for telecommunications
                      97-17R.W. HartensteinData scheduling to increase performance of parallel accelerators
                      97-18David GreenfieldEnhancing fixed point DSP processor performance by adding CPLDs as coprocessing elements
                      97-19Brad L. HutchingsExploiting reconfigurability through domain-specific systems
                      97-20Gordon McGregorExtending dynamic circuit switching to meet the challenges of new FPGA architectures
                      97-21Andreas DandalisFast parallel implementation of DFT using configurable devices
                      97-22C. C. JongFPGA implementation of a digital IQ demodulator using VHDL
                      97-23Arnaud TisserandFPGA implementation of real-time digital controllers using on-line arithmetic
                      97-24R. Bruce MaunderFPLD HDL synthesis employing high-level evolutionary algorithm optimisation
                      97-25Ian PageHardware compilation, configurable platforms and ASICs for self-validating sensors
                      97-26T.-T. DoImplementation of pipelined multipliers on Xilinx FPGAs
                      97-27Julio FauraMulticontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor
                      97-28Ilija HadzicP4: A platform for FPGA implementation of protocol boosters
                      97-29Barry RisingParallel graph colouring using FPGAs
                      97-30John M. EmmertPartial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement
                      97-31David RobinsonPerformance evaluation of a full speed PCI initiator and target subsystem using FPGAs
                      97-32W. LukPipeline morphing and virtual pipelines
                      97-33Satnam SinghPostScript rendering with virtual hardware
                      97-34Paul DunnReal-time stereopsis using FPGAs
                      97-35Patrick I. MackinlayRiley-2: A flexible platform for codesign and dynamic reconfigurable computing research
                      97-36Miriam LeeserRothko: A three dimensional FPGA architecture, its fabrication, and design tools
                      97-37Oliver DiesselRun-time compaction of FPGA designs
                      97-38Rob PayneRun-time parameterised circuits for the Xilinx XC6200
                      97-39Miron AbramoviciSatisfiability on reconfigurable hardware
                      97-40Brian KahneStream synthesis for a wormhole run-time reconfigurable platform
                      97-41B. LaurentStructural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA
                      97-42Michal Z. ServitTechnology mapping by binate covering
                      97-43Maurce Kilavuka InuaniTechnology mapping of heterogeneous LUT-based FPGAs
                      97-44Xiaochun LinTechnology mapping of LUT based FPGAs for delay optimisation
                      97-45Klaus FeskeTechnology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs
                      97-46Eric LechnerThe Java environment for reconfigurable computing
                      97-47Stuart NisbetThe XC6200DS development system
                      97-48Eduardo BoemoThermal monitoring on FPGAs using ring-oscillators
                      97-49Patrick LysaghtTowards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic
                      97-50B. BramerVirtual radix array processors (V-RaAP)
                      97-51Vaughn BetzVPR: A new packing, placement and routing tool for FPGA research

                    • eecejk
                      1998 paper list 98-1 J. Fischer A co-simulator concept for efficient analysis of complex logic designs 98-2 L. Lagadec A 6200 model and editor based on object
                      Message 10 of 26 , Feb 9, 2015
                        1998 paper list

                        98-1J. FischerA co-simulator concept for efficient analysis of complex logic designs
                        98-2L. LagadecA 6200 model and editor based on object technology
                        98-3Tsutomu MaruyamaA field-programmable gate-array system for evolutionary computation
                        98-4Tien-Toan DoA flexible implementation of high-performance FIR filters on xilinx FPGAs
                        98-5Tsunemichi ShiozawaA hardware implementation of constraint satisfaction problem based on new reconfigurable LSI architecture
                        98-6Pedro MerinoA hardware operating system for dynamic reconfiguration of FPGAs
                        98-7Gordon McGregorA hardware/software co-design environment for reconfigurable logic systems
                        98-8Neil W. BergmannA high-performance computing module for a low earth orbit satellite using reconfigurable logic
                        98-9Helena KrupnovaA knowledge-based system for prototyping on FPGAs
                        98-10N. L. MillerA novel field programmable gate array architecture for high speed arithmetic processing
                        98-11W. LukA reconfigurable engine for real-time video processing
                        98-12B. RadunovicA survey of reconfigurable computing architectures
                        98-13Toshoaki MiyazakiA transmutable telecom system
                        98-14Donald MacVicarAccelerating DTP with reconfigurable computing engines
                        98-15Marco PlatznerAcceleration of satisfiability algorithms by reconfigurable hardware
                        98-16Frank-Michael RennerAn FPGA implementation of a magnetic bearing controller for mechatronic applications
                        98-17Ali ZakerolhosseiniAn FPGA-based object recognition machine
                        98-18Gordon BrebnerAn interactive datasheet for the Xilinx XC6200
                        98-19Jörn StohmannAn optimized flow for fast FPGA-based rapid prototyping
                        98-20Samary BaranovCAD system for ASM and FSM synthesis
                        98-21Dominique LavenierComputing Goldbach partitions using pseudo-random bit generator operators on an fpga systolic array
                        98-22Béla FehérCost effective 2x2 inner product processors
                        98-23Reiner W. HartensteinDesigning for Xilinx XC6200 FPGAs
                        98-24Nicholas McKayDynamic specialization of XC6200 FPGAs by partial evaluation
                        98-25Stephen CharlwoodEvaluation of XC6200-series architecture for cryptographic applications
                        98-26R. W. HartensteinExploiting contemporary memory techniques in reconfigurable accelerators
                        98-27Neil WoolfriesFast adaptive image processing in FPGAs using stack filters
                        98-28John M. EmmertFast floorplanning for FPGAs
                        98-29Tero RissaFast prototyping using system emulators
                        98-30Gordon BrebnerField-programmable logic: Catalyst for new computing paradigms
                        98-31James HwangGenerating layouts for self-implementing modules
                        98-32C. N. Ojeda-GuerraHardware mapping of a parallel algorithm for matrix-vector multiplication overlapping communications and computations
                        98-33Elena Cerro-PradaHigh speed low level image processing on FPGAs using distributed arithmetic
                        98-34Rainer KressHigh-level synthesis for dynamically reconfigurable hardware/software systems
                        98-35István VassányiImplementing processor arrays on FPGAs
                        98-36Sergej SawitzkiIncreasing microprocessor performance with tightly-coupled reconfigurable logic arrays
                        98-37Timothy J. CallahanInstruction-level parallelism for reconfigurable computing
                        98-38Valery SklyarovIntegrated development environment for logic synthesis based on dynamically reconfigurable FPGAs
                        98-39M. EisenringInterfacing hardware and software
                        98-40Robert MacketanzJVX - a rapid prototyping system based on Java and FPGAs
                        98-41Shinichi YamagiwaMaestro-link: A high performance interconnect for PC cluster
                        98-42Kiran BondalapatiMapping loops onto reconfigurable architectures
                        98-43Jüri PõldreModular exponent realization on FPGAs
                        98-44David RobinsonNew CAD framework extends simulation of dynamically reconfigurable logic
                        98-45Georg AcherPCI-CSI protocol translations: Applying microprogramming concepts to FPGAs
                        98-46Wayne LukPebble: A language for parameterized and reconfigurable hardware design
                        98-47Jürgen BeckerPerspectives of reconfigurable computing in research, industry and education
                        98-48Andrej TrostProgrammable prototype system for image processing
                        98-49Andreas C. DöringProgramming and implementation of reconfigurable routers
                        98-50Joy ShelterPrototyping new ILP architectures using FPGAs
                        98-51Dinesh BhatiaREACT: Reactive environment for runtime reconfiguration
                        98-52Scott H. RobinsonReconfigurable computer array: The bridge between high speed sensors and low speed computing
                        98-53Samuel HolmströmReconfigurable hardware - a study in codesign
                        98-54Gunter HaugReconfigurable hardware as shared resource in multipurpose computers
                        98-55A. Abo ShoshaReconfigurable PCI-BUS interface (RPCI)
                        98-56N. ShiraziRun-time management of dynamically reconfigurable designs
                        98-57Adam DonlinSelf modifying circuitry - a platform for tractable virtual circuitry
                        98-58A. TouhafiSimulation of ATM switches using dynamically reconfigurable FPGA's
                        98-59Peixin ZhongSolving boolean satisfiability with dynamic hardware configurations
                        98-60Andreas DandalisSpace-efficient mapping of 2D-DCT onto dynamically configurable coarse-grained architectures
                        98-61Sameh AsaadSpeed optimization of the ALR circuit using an FPGA with embedded RAM: A design experience
                        98-62M. RenovellSRAM-based FPGAs: A fault model for the configurable logic modules
                        98-63Claude AckadStatechart-based HW/SW-codesign of a multi-FPGA-board and microprocessor
                        98-64Valeri TomachevThe PLD-implementation of boolean function characterized by minimum delay
                        98-65Christian SiemersThe s-puter: Introducing a novel concept for dispatching instructions using reconfigurable hardware
                        98-66María José MoureVirtual instruments based on reconfigurable logic
                        98-67Steven A. GuccioneWebScope: A circuit debug tool
                        98-68I. LemberskiXILINX4000 architecture - driven synthesis for speed

                      • eecejk
                        1999 paper list 99-1 E. Cantó A bipartitioning algorithm for dynamic reconfigurable programmable logic 99-2 Sergej Sawitzki A concept for an evaluation
                        Message 11 of 26 , Feb 9, 2015
                          1999 paper list

                          99-1E. CantóA bipartitioning algorithm for dynamic reconfigurable programmable logic
                          99-2Sergej SawitzkiA concept for an evaluation framework for reconfigurable systems
                          99-3Craig SlorachA distributed, scalable, multi-layered approach to evolvable system design using FPGA's
                          99-4Juanjo NogueraA HW/SW codesign-based reconfigurable environment for telecommunication network simulation
                          99-5M. Imran MasudA new switch block for segmented FPGAs
                          99-6M. BögeA processor for artificial life simulation
                          99-7Tsutomu MaruyamaA reconfigurable architecture for high speed computation by pipeline processing
                          99-8Wong Hiu YungA runtime reconfigurable implementation of the GSAT algorithm
                          99-9Philip James-RoxbyA wildcarding mechanism for acceleration of partial configurations
                          99-10Kolja SulimmaAccelerating boolean implications with FPGAs
                          99-11T. KuberkaAHA-GRAPE: Adaptive hydrodynamic architecture - gravity pipe
                          99-12María D. ValdésAn alternative solution for reconfigurable coprocessors hardware and interface synthesis
                          99-13Tomas DulikAn FPGA implementation of Goertzel algorithm
                          99-14Holger KroppAn FPGA-based prototyping system for real-time verification of video processing schemes
                          99-15Reiner W. HartensteinAn internet based development framework for reconfigurable computing
                          99-16Arnaud TisserandAn on-line arithmetic based FPGA for low-power custom computing
                          99-17Silviu M. S. A. ChiricescuAnalysis and optimization of 3-d FPGA design parameters
                          99-18M. BruckeAuditory signal processing in hardware: A linear gammatone filterbank design for a model of the auditory system
                          99-19Michael EisenringCommunication synthesis for reconfigurable embedded systems
                          99-20Rainer KressDebugging application-specific programmable products
                          99-21Malachy DevlinDIME - the first module standard for FPGA based high performance computing
                          99-22Kiran BondalapatiDRIVE: An interpretive simulation and visualization environment for dynamically reconfigurable systems
                          99-23Tri CaohuuDynamically reconfigurable reduced crossbar: a novel approach to large scale switching
                          99-24Milan VasilkoDYNASTY: A temporal floorplanning based CAD framework for dynamically reconfigurable logic systems
                          99-25Emanuel M. PopoviciFPGA design trade-offs for solving the key equation in Reed-Solomon decoding
                          99-26Ilija HadzicFPGA viruses
                          99-27Reetinder P. S. SidhuGenetic programming using self-reconfigurable FPGAs
                          99-28Martin DanekGlobal routing models
                          99-29Tsutomu MaruyamaHardware implementation techniques for recursive calls and loops
                          99-30Karam S. ChathaHardware-software codesign for dynamically reconfigurable architectures
                          99-31Helena KrupnovaHierarchical interactive approach to partition large designs into FPGAs
                          99-32Keith J. SymingtonHigh bandwidth dynamically reconfigurable architectures using optical interconnects
                          99-33R. B. MaunderHigh-level hierarchical HDL synthesis of pipelined FPGA-based circuits using synchronous modules
                          99-34Stefan LudwigImplementing photoshop filters in Virtex
                          99-35Steve CasselmanIp validation for FPGAs using hardware object technologytm
                          99-36Valeri F. TomashauLogic circuit speeding up through multiplexing
                          99-37William K. C. HoLogical-to-physical memory mapping for FPGAs with dual-port embedded arrays
                          99-38R. HartensteinMapping applications onto reconfigurable kressarrays
                          99-39Markus WeinhardtMemory access optimization and ram inference for pipeline vectorization
                          99-40David RobinsonModelling and synthesis of configuration controllers for dynamically reconfigurable logic systems using the DCS CAD framework
                          99-41Dinesh BhatiaNEBULA: A partially and dynamically reconfigurable architecture
                          99-42Andreas KochOn tool integration in high-performance FPGA design flows
                          99-43Captain Gregory C. AhlquistOptimal finite field multipliers for FPGAs
                          99-44Iakovos StamoulisPipelined floating point arithmetic optimised for FPGA architectures
                          99-45Mathew WojkoPipelined multipliers and FPGA architectures
                          99-46Juan de VicentePlacement optimization based on global routing updating for system partitioning onto multi-FPGA mesh topologies
                          99-47Andrés GarciaPower modelling in field programmable gate arrays (FPGA)
                          99-48Gareth JonesPulseDSP - a signal processing oriented programmable architecture
                          99-49N. ShiraziQuantitative analysis of run-time reconfigurable database search
                          99-50Klaus FeskeRapid FPGA prototyping of a dab test data generator using protocol compiler
                          99-51Gordon BrebnerReconfigurable computing in remote and harsh environments
                          99-52Juri PõldreReconfigurable multiplier for Virtex FPGA family
                          99-53Paul GrahamReconfigurable processors for high-performance, embedded digital signal processing
                          99-54A. TouhafiReconfigurable programming in the large on extendable uniform reconfigurable computing array's: an integrated approach based on reconfigurable virtual architectures
                          99-55Donald MacVicarRendering postscript fonts on FPGAs
                          99-56Steven A. GuccioneRun-time parameterizable cores
                          99-57Bernardo KastrupSeeking (the right) problems for the solutions of reconfigurable computing
                          99-58Gordon McGregorSelf controlling dynamic reconfiguration
                          99-59W. LukSerial hardware libraries for reconfigurable designs
                          99-60Samuel HolmströmSL - a structural hardware design language
                          99-61Simon D. HaynesSONIC - a plug-in architecture for video processing
                          99-62Arnaldo OliveiraSpecification, implementation and testing of HFSMs in dynamically reconfigurable FPGAs
                          99-63George A. ConstantinidesSynthia: Synthesis of interacting automata targeting LUT-based FPGAs
                          99-64John M. Emmert Tabu search: Ultra-fast placement for FPGAs
                          99-65Michael DalesThe Proteus processor - a conventional CPU with reconfigurable functionality

                        • eecejk
                          2000 paper list 00-1 Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino A Co-processor System with a Virtex FPGA for Evolutionary
                          Message 12 of 26 , Feb 9, 2015
                            2000 paper list

                            00-1Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu HoshinoA Co-processor System with a Virtex FPGA for Evolutionary Computation
                            00-2Xue-Jie Zhang, Kam-Wing Ng, Wayne LukA Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
                            00-3Radhika S. Grover, Weijia Shang, Qiang LiA Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers
                            00-4Xinan TangA Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors
                            00-5Stephen J. Bellis, William P. MarnaneA CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System
                            00-6Johan DitmarA Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization
                            00-7Tero Rissa, Jarkko NiittylahtiA Hybrid Prototyping Platform for Dynamically Reconfigurable Designs
                            00-8Holger Kropp, Carsten ReuterA Mapping Methodology for Code Trees onto LUT-Based FPGAs
                            00-9Abdellah TouhafiA Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller
                            00-10Frank Wolz, Reiner KollaA New Floorplanning Method for FPGA Architectural Research
                            00-11M. Redekopp, Andreas DandalisA Parallel Pipelined SAT Solver for FPGAs
                            00-12Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev JayaramanA Placement Algorithm for FPGA Designs with Multiple I/O Standards
                            00-13André Brinkmann, Dominik Langen, Ulrich RückertA Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor
                            00-14Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu AmanoA Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems
                            00-15Reetinder P. S. SidhuA Self-Reconfigurable Gate Array Architecture
                            00-16Michel RenovellA Specific Test Methodology for Symmetric SRAM-Based FPGAs
                            00-17Rolf Hoffmann, Bernd Ulmann, Klaus-Peter Völkmann, Stefan WaldschmidtA Stream Processor Architecture Based on the Configurable CEPRA-S
                            00-18Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo NakajimaA Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology
                            00-19Jens Hildebrandt, Dirk TimmermannAn FPGA based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems
                            00-20Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi NakadaAn Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture
                            00-21Uwe Hatnik, Jürgen Haufe, Peter SchwarzAn Innovative Approach to Couple EDA Tools with Reconfigurable Hardware
                            00-22Javier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-RuízAnalysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform
                            00-23Srini Krishnamoorthy, Sriram Swaminathan, Russell TessierArea-Optimized Technology Mapping for Hybrid FPGAs
                            00-24Milan Vasilko, Graham Benyon-TinkerAutomatic Temporal Floorplanning with Guaranteed Solution Feasibility
                            00-25Russell Tessier, Heather GizaBalancing Logic Utilization and Area Efficiency in FPGAs
                            00-26Oliver Diessel, George J. MilneBehavioural Language Compilation with Virtual Hardware Management
                            00-27Arran Derbyshire, Wayne LukCombining Serialisation and Reconfiguration for FPGA Designs
                            00-28Joerg Abke, Erich BarkeCoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs
                            00-29Selene Maya, Rocio Reynoso, Cesar Torres-Huitzil, Miguel Arias-EstradaCompact Spiking Neural Network Implementation in FPGA
                            00-30Bernardo Kastrup, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, Jef L. van MeerbergenCompiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis
                            00-31Juanjo Noguera, Rosa M. BadiaConfiguration Prefetching for Non-deterministic Event Driven Multi-context Schedulers
                            00-32Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu AmanoDataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware
                            00-33Alexander Glasmacher, Kai WoskaDesign and Implementation of an XC6216 FPGA Model in Verilog
                            00-34T. BartzickDesign of a Fault Tolerant FPGA
                            00-35Milan VasilkoDesign Visualisation for Dynamically Reconfigurable Systems
                            00-36Jürgen Becker, Thilo Pionteck, Manfred GlesnerDReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications
                            00-37Andrej Trost, Andrej Zemva, Baldomir ZajcEducational Programmable Hardware Prototyping and Verification System
                            00-38Christophe Bobda, Thomas LehmannEfficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction
                            00-39Sushil Chandra Jain, Anshul Kumar, Shashi KumarEfficient Embedding of Partitioned Circuits onto Multi-FPGA Boards
                            00-40Sameer Wadhwa, Andreas DandalisEfficient Self-Reconfigurable Implementations Using On-chip Memory
                            00-41Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji KonishiEvaluation of Accelerator Designs for Subgraph Isomorphism Problem
                            00-42Andrzej KrasniewskiExploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs
                            00-43Alfred Blaickner, O. Nagy, Herbert GrünbacherFast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic
                            00-44Frank-Michael RennerField Programmable Communication Emulation and Optimization for Embedded System Design
                            00-45Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd StraubeFormal Verification of a Reconfigurable Microprocessor
                            00-46Winnie W. Cheng, Steven J. E. Wilton, Babak HamidzadehFPGA Implementation of a Prototype WDM On-Line Scheduler
                            00-47Bogdan Matasaru, Tudor JebeleanFPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers
                            00-48Helena KrupnovaFPGA-Based Emulation: Industrial and Custom Prototyping Solutions
                            00-49Rainer KressFPGA-Based Prototyping for Product Definition
                            00-50Kalle Tammemäe, T. EvartsonFPL Curriculum at Tallinn Technical University
                            00-51John S. McCaskill, Patrick WaglerFrom Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains
                            00-52Andreas C. Döring, Gunther LustigGenerating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory
                            00-53Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich NageldingerGeneration of Design Suggestions for Coarse-Grain Reconfigurable Architectures
                            00-54Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu HoshinoHigh Speed Computation of Lattice gas Automata with FPGA
                            00-55Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard TrösterHigh-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
                            00-56E. CantóImplementation of Virtual Circuits by Means of the FIPSOC Devices
                            00-57G. LíasImplementing a Fieldbus Interface Using an FPGA
                            00-58Jihan Zhu, George J. MilneImplementing Kak Neural Networks on a Reconfigurable Computing Platform
                            00-59Hamish FallsideInternet Connected FPL
                            00-60Tom KeanIt's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures
                            00-61Paul M. Heysters, Jaap Smit, Gerard J. M. Smit, Paul J. M. HavingaMapping of DSP Algorithms on Field Programmable Function Arrays
                            00-62Holger Lange, Andreas KochMemory Access Schemes for Configurable Processors
                            00-63Petr PfeiferMultifunctional Programmable Single-Board CAN Monitoring Module
                            00-64George A. Constantinides, Peter Y. K. Cheung, Wayne LukMultiple-Wordlength Resource Binding
                            00-65Tim Courtney, Richard H. Turner, Roger WoodsMultiplexer Based Reconfiguration for Virtex Multipliers
                            00-66Harald SimmlerMultitasking on FPGA Coprocessors
                            00-67A. Hilton, J. HallOn Applying Software Development Best Practice to FPFAs in Safety Critical Systems
                            00-68Darko Stefanovic, Margaret MartonosiOn Availability of Bit-Narrow Operations in General-Purpose Applications
                            00-69Michael Eisenring, Marco PlatznerOptimization of Run-Time Reconfigurable Embedded Systems
                            00-70Jian Qiao, Makoto Ikeda, Kunihiro AsadaOptimum Functional Decomposition for LUT-Based FPGA Synthesis
                            00-71Scott McMillan, Steve GuccionePartial Run-Time Reconfiguration Using JRTR
                            00-72John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron AbramoviciPerformance Penalty for Fault Tolerance in Roving STARs
                            00-73Erwan Fabiani, Dominique LavenierPlacement of Linear Arrays
                            00-74Jim TorresenPossibilities and Limitations of Applying Evolvable Hardware to Real-World Applications
                            00-75Brandon BlodgetPre-route Assistant: A Routing Tool for Run-Time Reconfiguration
                            00-76Guy Lecurieux LafayetteProgrammable System Level Integration Brings System-on-Chip Design to the Desktop
                            00-77Rob McCreadyReal-Time Face Detection on a Configurable Hardware System
                            00-78Christian SiemersReconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling
                            00-79Stephen J. Melnikoff, Philip James-Roxby, Steven F. Quigley, Martin J. RussellReconfigurable Computing for Speech Recognition: Preliminary Findings
                            00-80Marios IliopoulosReconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits
                            00-81Hideharu Amano, Yuichiro Shibata, Masaki UnoReconfigurable Systems: New Activities in Asia
                            00-82Jernej Andrejas, Andrej TrostReusable DSP Functions in FPGAs
                            00-83Hagen Ploog, Mathias Schmalisch, Dirk TimmermannSecurity Upgrade of Existing ISDN Devices by Using Reconfigurable Logic
                            00-84Pawel TomaszewiczSelf-Testing of Linear Segments in User-Programmed FPGAs
                            00-85Jan M. RabaeySilicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play?
                            00-86Xavier Revés, Antoni Gelonch, Ferran Casadevall, José L. GarcíaSoftware Radio Reconfigurable Hardware System (SHaRe)
                            00-87Jörn GauseStatic and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT
                            00-88Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHonStream Computations Organized for Reconfigurable Execution (SCORE)
                            00-89Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. FlynnStReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
                            00-90Valery SklyarovSynthesis and Implementation of RAM-Based Finite State Machines in FPGAs
                            00-91Christine Bauer, Peter Zipf, Hans WojtkowiakSystem Design with Genetic Algorithms
                            00-92Hossam A. ElGindy, Martin Middendorf, Hartmut Schmeck, Bernd SchmidtTask Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer
                            00-93Takahiro Miomo, Koichi Yasuoka, Masanori KanazawaThe Fastest Multiplier on FPGAs with Redundant Binary Representation
                            00-94Martyn Edwards, Peter GreenThe Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware
                            00-95Jean-Michel Raczinski, Stéphane SladekThe Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing
                            00-96Tsugio MakimotoThe Rising Wave of Field Programmability
                            00-97Rafael Gadea Gironés, Vicente Herrero, Angel Sebastia, Antonio Mocholí SalcedoThe Role of the Embedded Memories in the Implementation of Artificial Neural Networks
                            00-98Sriram GovindarajanTightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS
                            00-99Lukás Sekanina, Azeddien M. SllameToward Uniform Approach to Design of Evolvable Hardware Based Systems
                            00-100David RobinsonVerification of Dynamically Reconfigurable Logic
                            00-101Chris PhillipsWireless Base Station Design Using a Reconfigurable Communications Processor

                          • eecejk
                            2001 paper list 01-1 Ram Subramanian, Santosh Pande A Data Re-use Based Compiler Optimization for FPGAs 01-2 Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk
                            Message 13 of 26 , Feb 9, 2015
                              2001 paper list

                              01-1Ram Subramanian, Santosh PandeA Data Re-use Based Compiler Optimization for FPGAs
                              01-2Chakkapas Visavakul, Peter Y. K. Cheung, Wayne LukA Digit-Serial Structure for Reconfigurable Multipliers
                              01-3Tilman Neumann, Andreas KochA Generic Library for Adaptive Computing Environments
                              01-4Takashi Saito, Tsutomu Maruyama, Tsutomu Hoshino, Saburo HiranoA Music Synthesizer on FPGA
                              01-5Oswaldo Cadenas, Graham M. MegsonA n-Bit Reconfigurable Scalar Quantiser
                              01-6Joerg Abke, Erich BarkeA New Placement Method for Direct Mapping into LUT-Based FPGAs
                              01-7Raymond Sinnappan, Scott HazelhurstA Reconfigurable Approach to Packet Filtering
                              01-8Apostolos Dollas, Kyprianos Papademetriou, Nikolaos Aslanides, Tom KeanA Reconfigurable Embedded Input Device for Kinetically Challenged Persons
                              01-9Isidoro Urriza, José I. García-Nicolás, Alfredo Sanz, Antonio ValdovinosA System on Chip for Power Line Communications According to European Home Systems Specifications
                              01-10Abbes Amira, Ahmed Bouridane, Peter MilliganAccelerating Matrix Product on Reconfigurable Hardware for Signal Processing
                              01-11Tsutomu Maruyama, Yoshiki Yamaguchi, Atsushi KawaseAn Approach to Real-Time Visualization of PIV Method with FPGA
                              01-12Chris Fisher, Kevin Rennie, Guanbin Xing, Stefan G. Berg, Kevin Bolding, John H. Naegle, Daniel Parshall, Dmitriy Portnov, Adnan Sulejmanpasic, Carl EbelingAn Emulator for Exploring RaPiD Configurable Computing Architectures
                              01-13Cristian Ciressan, Eduardo Sanchez, Martin Rajman, Jean-Cédric ChappelierAn FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars
                              01-14Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki KajiharaArithmetic Operation Oriented Reconfigurable Chip: RHW
                              01-15Frank Wolz, Reiner KollaBubble Partitioning for LUT-Based Sequential Circuits
                              01-16Eric KellerBuilding Asynchronous Circuits with JBits
                              01-17Thomas Lehmann, Andreas SchreckenbergCase Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux
                              01-18Gordon J. Brebner, Oliver DiesselChip-Based Reconfigurable Task Management
                              01-19João M. P. Cardoso, Horácio C. NetoCompilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
                              01-20Suraj Sudhir, Suman Nath, Seth Copen GoldsteinConfiguration Caching and Swapping
                              01-21Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy LauwereinsCRISP: A Template for Reconfigurable Instruction Set Processors
                              01-22Albert Simpson, Jill K. Hunter, Moira Wylie, Yi Hu, David MannDemonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing
                              01-23Nikolaus Voß, Bärbel MertschingDesign and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware
                              01-24Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De ManDevelopment of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware
                              01-25Matti Tommiska, Jorma SkyttäDijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware
                              01-26John MacBeth, Patrick LysaghtDynamically Reconfigurable Cores
                              01-27Michael J. Wirthlin, Brian McMurtreyEfficient Constant Coefficient Multiplication Using Advanced FPGA Architectures
                              01-28Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred GlesnerEfficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures
                              01-29Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. ChanEvaluation of an FPGA Implementation of the Discrete Element Method
                              01-30PariVallal Kannan, Shankar Balachandran, Dinesh BhatiafGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits
                              01-31Kent E. Wires, Michael J. Schulte, Don McCarleyFPGA Resource Reduction Through Truncated Multiplication
                              01-32Mokhtar Nibouche, Ahmed Bouridane, Fionn Murtagh, Omar NiboucheFPGA-Based Discrete Wavelet Transforms System
                              01-33Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo ViolanteFPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
                              01-34Riad Stefo, Jose Luis Nunez, Claudia Feregrino, Sudipta Mahapatra, Simon R. JonesFPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding
                              01-35John Karro, James P. CohoonGambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays
                              01-36Stephan Rühl, Peter Dillinger, Stefan Hezel, Reinhard MännerGenerative Development System for FPGA Processors with Active Components
                              01-37Bryan S. Goda, Russell P. Kraft, Steven R. Carlough, Thomas W. Krawczyk Jr., John F. McDonaldGigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs
                              01-38Jim Harkin, T. Martin McGinnity, Liam P. MaguireHardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach
                              01-39Felix Albu, Jiri Kadlec, Christopher I. Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman, Anthony D. FaganImplementation of (Normalised) RLS Lattice on Virtex
                              01-40Paula N. Mallón, Montserrat Bóo, Javier D. BrugueraImplementation of a NURBS to Bézier Conversor with Constant Latency
                              01-41Stephen J. Melnikoff, Steven F. Quigley, Martin J. RussellImplementing a Hidden Markov Model Speech Recognition System in Programmable Logic
                              01-42Michael DalesInitial Analysis of the Proteus Architecture
                              01-43Scott McMillan, Cameron PattersonJBitsTM Implementations of the Advanced Encryption Standard (Rijndael)
                              01-44Steven Derrien, Sanjay V. RajopadhyeLoop Tiling for Reconfigurable Accelerators
                              01-45Ernie Lin, Steven J. E. WiltonMacrocell Architectures for Product Term Embedded Memory Arrays
                              01-46Amit Kasat, Iyad Ouaiss, Ranga VemuriMemory Synthesis for FPGA-Based Reconfigurable Computers
                              01-47Shervin Sheidaei, Hamid Noori, Ahmad Akbari, Hossein PedramMotivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders
                              01-48Miguel Arias-Estrada, Juan M. XicotencatlMultiple Stereo Matching Using an Extended Architecture
                              01-49Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry StylesParameterized Function Evaluation for FPGAs
                              01-50Loïc Lagadec, Dominique Lavenier, Erwan Fabiani, Bernard PottierPlacing, Routing, and Editing Virtual FPGAs
                              01-51Jeff LawrenceProcessing Models for the Next Generation Network [Abstract]
                              01-52Sergej Sawitzki, Steffen Köhler, Rainer G. SpallekPrototyping Framework for Reconfigurable Processors
                              01-53Klaus Harbich, Erich BarkePuMA++: From Behavioral Specification to Multi-FPGA-Prototype
                              01-54Satnam Singh, Philip James-RoxbyRapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits
                              01-55Jerzy KasperekReal Time Morphological Image Contrast Enhancement in Virtex FPGA
                              01-56Tim Price, Cameron PattersonReconfigurable Breakpoints for Co-debug
                              01-57Sergio A. Cuenca, Francisco Ibarra, Rafael ÁlvarezReconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems
                              01-58Florian Braun, John W. Lockwood, Marcel WaldvogelReconfigurable Router Modules Using Network Protocol Wrappers
                              01-59Marios Iliopoulos, Theodore AntonakopoulosRun-Time Optimized Reconfiguration Using Instruction Forecasting
                              01-60Andreas Dandalis, Viktor K. Prasanna, Bharani ThiruvengadamRun-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers
                              01-61Tom KeanSecure Configuration of Field Programmable Gate Arrays
                              01-62Máire McLoone, John V. McCannySingle-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm
                              01-63Srihari Cadambi, Seth Copen GoldsteinStatic Profile-Driven Compilation for FPGAs
                              01-64Michael J. Wirthlin, Brad L. Hutchings, Carl WorthSynthesizing RTL Hardware from Java Byte Codes
                              01-65James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey D. StroomerSystem Level Tools for DSP in FPGAs
                              01-66Markus Weinhardt, Wayne LukTask-Parallel Programming of Reconfigurable Systems
                              01-67Michael J. Flynn, Albert A. LiddicoatTechnology Trends and Adaptive Computing
                              01-68Bill CarterThe Evolution of Programmable Logic: Past, Present, and Future Predictions [Abstract]
                              01-69Stamatis Vassiliadis, Stephan Wong, Sorin CotofanaThe MOLEN rho-mu-Coded Processor
                              01-70Gilles Sassatelli, Lionel Torres, Jérôme Galy, Gaston Cambon, Camille DiouThe Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems
                              01-71PariVallal Kannan, Dinesh BhatiaTightly Integrated Placement and Routing for FPGAs
                              01-72Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. HutchingsUsing Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification
                              01-73Lok-Kee Ting, Roger Woods, Colin CowanVirtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver
                              01-74Jose Luis Nunez, Claudia Feregrino, Simon R. Jones, Stephen BatemanX-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor

                            • eecejk
                              2002 paper list 02-1 Issam Damaj, Sohaib Majzoub, Hassan B. Diab 2D and 3D Computer Graphics Algorithms under MORPHOSYS 02-2 Antti Hämäläinen, Matti
                              Message 14 of 26 , Feb 9, 2015
                                2002 paper list

                                02-1Issam Damaj, Sohaib Majzoub, Hassan B. Diab2D and 3D Computer Graphics Algorithms under MORPHOSYS
                                02-2Antti Hämäläinen, Matti Tommiska, Jorma Skyttä8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm
                                02-3Oswaldo Cadenas, Graham M. MegsonA Clocking Technique with Power Savings in Virtex-Based Pipelined Designs
                                02-4Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier SentieysA Compilation Framework for a Dynamically Reconfigurable Architecture
                                02-5Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier LegatA Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation
                                02-6Kara K. W. Poon, Andy Yan, Steven J. E. WiltonA Flexible Power Model for FPGAs
                                02-7Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred GlesnerA Framework for Teaching (Re)Configurable Architectures in Student Projects
                                02-8Naoto Kaneko, Hideharu AmanoA General Hardware Design Model for Multicontext FPGAs
                                02-9Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi YoshidaA Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model
                                02-10Spyros Blionas, Kostas Masselos, Chrissavgi Dre, Christos Drosos, F. Z. Ieromnimon, T. Pagonis, A. Pneymatikakis, Anna Tatsaki, T. Trimis, A. Vontzalidis, Dimitris MetafasA HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip
                                02-11Pavle Belanovic, Miriam LeeserA Library of Parameterized Floating-Point Modules and Their Use
                                02-12Alex Carreira, Trevor W. Fox, Laurence E. TurnerA Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM
                                02-13Dylan Carline, Paul CoultonA Novel Watermarking Technique for LUT Based FPGA Designs
                                02-14Akira Miyashita, Toshihito Fujiwara, Tsutomu MaruyamaA Placement/Routing Approach for FPGA Accelerators
                                02-15Khaled Benkrid, Danny Crookes, Abdsamad Benkrid, S. BelkacemiA Prolog-Based Hardware Development Environment
                                02-16Domingo BenitezA Quantitative Understanding of the Performance of Reconfigurable Coprocessors
                                02-17Adronis Niyonkuru, Göran Eggers, Hans Christoph ZeidlerA Reconfigurable Processor Architecture
                                02-18Sebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus KünanzA Reconfigurable System-on-Chip-Based Fast EDM Process Monitor
                                02-19Frank Wolz, Reiner KollaA Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures
                                02-20Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. StrolloA Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations
                                02-21Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. BoemoA Tool for Activity Estimation in FPGAs
                                02-22Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De ManAdding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
                                02-23Anna Labbé, Annie PérezAES Implementation on FPGA: Time - Flexibility Tradeoff
                                02-24Massimo Baleani, Massimo Conti, Alberto Ferrari, Valerio Frascolla, Alberto L. Sangiovanni-VincentelliAn Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms
                                02-25Kurt K. Ting, Steve C. L. Yuen, Kin-Hong Lee, Philip Heng Wai LeongAn FPGA Based SHA-256 Processor
                                02-26Miguel Arias-Estrada, Eduardo Rodríguez-PalaciosAn FPGA Co-processor for Real-Time Visual Tracking
                                02-27Zbigniew Kokosinski, Wojciech SikoraAn FPGA Implementation of a Multi-comparand Multi-search Associative Processor
                                02-28François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier LegatAn FPGA Implementation of the Linear Cryptanalysis
                                02-29Roberto Gaudino, Vito De Feo, Marcello Chiaberge, Claudio SansoèAn FPGA-based Node Controller for a High Capacity WDM Optical Packet Network
                                02-30Guy G. Lemieux, David M. LewisAnalytical Framework for Switch Block Design
                                02-31George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios ThanailakisArchitecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations
                                02-32Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. VranesicAutomatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
                                02-33Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James HwangAutomating Customisation of Floating-Point Designs
                                02-34James Hwang, Jonathan BallaghBuilding Custom FIR Filters Using System Generator
                                02-35Ivo BolsensChallenges and Opportunities for FPGA Platforms
                                02-36Mihai Budiu, Seth Copen GoldsteinCompiling Application-Specific Hardware
                                02-37Rudy LauwereinsCreating a World of Smart Re-configurable Devices
                                02-38Abbes Amira, Ahmed Bouridane, Peter Milligan, Faycal BensaaliCustom Coprocessor Based Matrix Algorithms for Image and Signal Processing
                                02-39José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João MouraDARP - A Digital Audio Reconfigurable Processor
                                02-40Shuichi Ichikawa, Shoji YamamotoData Dependent Circuit for Subgraph Isomorphism Problem
                                02-41Masayuki Kirimura, Yoshifumi Takamoto, Takanori Mori, Keiichi Yasumoto, Akio Nakata, Teruo HigashinoDesign and Implementation of FPGA Circuits for High Speed Network Monitors
                                02-42Reiner W. HartensteinDisruptive Trends by Data-Stream-Based Computing
                                02-43Ernest Jamro, Kazimierz WiatrDynamic Constant Coefficient Convolvers Implemented in FPGAs
                                02-44Gerard J. M. Smit, Paul J. M. Havinga, Lodewijk T. Smit, Paul M. Heysters, Michèl A. J. RosienDynamic Reconfiguration in Mobile Systems
                                02-45Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich RückertDynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations
                                02-46Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre, Vicente Torres-CarotEfficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard
                                02-47Reetinder P. S. Sidhu, Viktor K. PrasannaEfficient Metacomputation Using Self-Reconfiguration
                                02-48Katarzyna Leijten-Nowak, Jef L. van MeerbergenEmbedded Reconfigurable Logic Core for DSP Applications
                                02-49Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio ZamboniEnergy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor
                                02-50Ju-wook Jang, Seonil Choi, Viktor K. PrasannaEnergy-Efficient Matrix Multiplication on FPGAs
                                02-51Andrzej KrasniewskiExploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs
                                02-52Jan Schmidt, Martin Novotný, Martin Jäger, Milos Becvár, Michal JáchimExploration of Design Space in ECDSA
                                02-53Girish Venkataramani, Suraj Sudhir, Mihai Budiu, Seth Copen GoldsteinFactors Influencing the Performance of a CPU-RFU Hybrid Architecture
                                02-54Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza EjlaliFast Prototyping with Co-operation of Simulation and Emulation
                                02-55Channakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonaldFast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques
                                02-56Tyson S. Hall, Paul E. Hasler, David V. AndersonField-Programmable Analog Arrays: A Floating-Gate Approach
                                02-57Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. VissersField-Programmable Custom Computing Machines - A Taxonomy
                                02-58Katherine Compton, Akshay Sharma, Shawn Phillips, Scott HauckFlexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems
                                02-59Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred GlesnerFly - A Modifiable Hardware Compiler
                                02-60Francis Calmon, M. Fathallah, P. J. Viverge, Christian Gontrand, Jordi Carrabina, P. FoussierFPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms
                                02-61Antony Jamin, Petri MähönenFPGA Implementation of the Wavelet Packet Transform for High Speed Communications
                                02-62Chris Dick, Fred HarrisFPGA QAM Demodulator Design
                                02-63Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. BoemoFSM Decomposition for Low Power in FPGA
                                02-64Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick:Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2)
                                02-65Steve Guccione, Eric KellerGene Matching Using JBits
                                02-66Filip Miletic, Rene van Leuken, Alexander de GraafGeneral Purpose Prototyping Platform for Data-Processor Research and Development
                                02-67Maya Gokhale, Dave Dubois, Andy Dubois, Mike Boorman, Steve Poole, Vic HogsettGranidt: Towards Gigabit Rate Network Intrusion Detection Technology
                                02-68Oskar Mencer, Zhining Huang, Lorenz HuelsbergenHAGAR: Efficient Multi-context Graph Processors
                                02-69Peter Zipf, Manfred Glesner, Christine Bauer, Hans WojtkowiakHandling FPGA Faults and Configuration Sequencing Using a Hardware Extension
                                02-70Wolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jörg PfleidererHardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks
                                02-71Francisco Cardells-Tormo, Javier Valls-CoquillatHigh Performance Quadrature Digital Mixers for FPGAs
                                02-72Tomoyoshi Kobori, Tsutomu MaruyamaHigh Speed Computation of Three Dimensional Cellular Automata with FPGA
                                02-73Yoshiki Yamaguchi, Yosuke Miyajima, Tsutomu Maruyama, Akihiko KonagayaHigh Speed Homology Search Using Run-Time Reconfiguration
                                02-74Rafal Kielbik, Juan Manuel Moreno, Andrzej Napieralski, Grzegorz Jablonski, Tomasz SzymanskiHigh-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
                                02-75Helena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid MorsiHow Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project
                                02-76Gi-Joon Nam, Karem A. Sakallah, Rob A. RutenbarHybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
                                02-77Wim J. C. Melis, Peter Y. K. Cheung, Wayne LukImage Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer
                                02-78Viktor Fischer, Milos Drutarovský, Rastislav Lukac:Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware
                                02-79Thomas BuernerImplementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid Prototyping
                                02-80Alexander Staller, Peter Dillinger, Reinhard MännerImplementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
                                02-81Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin RollandImplementing Asynchronous Circuits on LUT Based FPGAs
                                02-82Alfredo Sanz, José I. García-Nicolás, Isidoro UrrizaImplementing Converters in FPLD
                                02-83Martin Henz, Edgar Tan, Roland H. C. YapImplementing CSAT Local Search on FPGAs
                                02-84Trevor W. Fox, Laurence E. TurnerImplementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA
                                02-85Ian Robertson, James Irvine, Patrick Lysaght, David RobinsonImproved Functional Simulation of Dynamically Reconfigurable Logic
                                02-86Martin Danek, Zdenek MuzikárIntegrated Iterative Approach to FPGA Placement
                                02-87Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander SedlmeierIntegration of Reconfigurable Hardware into System-Level Design
                                02-88Théodore Marescaux, Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy LauwereinsInterconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
                                02-89Grant B. Wigley, David A. Kearney, David WarrenIntroducing ReConfigME: An Operating System for Reconfigurable Computing
                                02-90Jawad Khan, Manish Handa, Ranga VemuriiPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications
                                02-91Rudolf Matousek, Milan Tichý, Zdenek Pohl, Jiri Kadlec, Christopher I. Softley, Nick ColemanLogarithmic Number System and Floating-Point Arithmetics on FPGA
                                02-92Uwe Meyer-Bäse, Javier Ramírez, Antonio GarcíaLow Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs
                                02-93Daniel G. Saab, Fatih Kocan, Jacob A. AbrahamMassively Parallel/Reconfigurable Emulation Model for the D-algorithm
                                02-94Aneesh Koorapaty, Lawrence T. PileggiModular, Fabric-Specific Synthesis for Programmable Architectures
                                02-95Silviu M. S. A. Chiricescu, Michael A. Schuette, Robin Glinton, Herman SchmitMorphable Multipliers
                                02-96Richard H. Turner, Roger Woods, Tim CourtneyMultiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs
                                02-97Wesley J. Landaker, Michael J. Wirthlin, Brad L. HutchingsMultitasking Hardware on the SLAAC1-V Reconfigurable Computing System
                                02-98Gordon J. BrebnerMultithreading for Logic-Centric Systems
                                02-99Eric Roesler, Brent E. NelsonNovel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
                                02-100Kai-Pui Lam, Sui-Tung MakOn Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach
                                02-101Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung CheungOn Optimum Designs of Universal Switch Blocks
                                02-102Andrzej KrasniewskiOn the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs
                                02-103Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. M. FerreiraOn-line Defragmentation for Run-Time Partially Reconfigurable FPGAs
                                02-104Nazeeh Aranki, Alexander Moopenn, Raoul TawelParallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform
                                02-105Matthias Dyer, Christian Plessl, Marco PlatznerPartially Reconfigurable Cores for Xilinx Virtex
                                02-106Joan Carletta, M. D. RaymanPractical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs
                                02-107PariVallal Kannan, Shankar Balachandran, Dinesh BhatiaRapid and Reliable Routability Estimation for FPGAs
                                02-108Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu BabaReal-Time Medical Diagnosis on a Multiple FPGA-based System
                                02-109Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli:REFLIX: A Processor Core for Reactive Embedded Applications
                                02-110Naoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu AmanoRHiNET/NI: A Reconfigurable Network Interface for Cluster Computing
                                02-111Emmanuel A. Moreira, Paul L. McAlpine, Simon D. HaynesRijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform
                                02-112Shay Ping Seng, Wayne Luk, Peter Y. K. CheungRun-Time Adaptive Flexible Instruction Processors
                                02-113Sergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. BoemoRun-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology
                                02-114Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. ChanScalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform
                                02-115Justin L. Tripp, Preston A. Jackson, Brad L. HutchingsSea Cucumber: A Synthesizing Compiler for FPGAs
                                02-116Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo ViolanteSimulation-Based Analysis of SEU Effects on SRAM-based FPGAs
                                02-117Jean-Luc Beuchat, Arnaud TisserandSmall Multiplier-Based Multiplication and Division Operators for Virtex-II Devices
                                02-118Klaus Feske, Georg Heinrich, Berndt Fritzsche, Mark LangerSoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications
                                02-119Stephanie McBader, Luca Clementel, Alvise Sartori, Andrea Boni, Peter LeeSoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor
                                02-120Sylvain Poussier, Hassan Rabah, Serge WeberSOPC-based Embedded Smart Strain Gage Sensor
                                02-121Young H. Cho, Shiva Navab, William H. Mangione-SmithSpecialized Hardware for Deep Network Packet Filtering
                                02-122Stephen J. Melnikoff, Steven F. Quigley, Martin J. RussellSpeech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models
                                02-123Stephen Charlwood, Jonathan Mangnall, Steven F. QuigleySystem-Level Modelling for Performance Estimation of Reconfigurable Coprocessors
                                02-124Lucídio dos Anjos Formiga Cabral, Júlio S. Aude, Nelson MaculanTDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs
                                02-125Paul MasterThe Age of Adaptive Computing Is Here
                                02-126Tuomas Valtonen, Jouni Isoaho, Hannu TenhunenThe Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance
                                02-127Ramaswamy Ramaswamy, Russell TessierThe Integration of SystemC and Hardware-Assisted Verification
                                02-128Kazuo Aoyama, Hiroshi SawadaThreshold Element-Based Symmetric Function Generators and Their Functional Extension
                                02-129Javier Ramírez, Antonio GarcíaU. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation
                                02-130Simon D. Haynes, Henry G. Epsom, Richard J. Cooper, Paul L. McAlpineUltraSONIC: A Reconfigurable Architecture for Video Image Processing
                                02-131Alireza KavianiUsing Design Hierarchy to Improve Quality of Results in FPGAs
                                02-132Edson L. Horta, John W. Lockwood, Sergio Takeo KofujiUsing PARBIT to Implement Partial Run-Time Reconfigurable Systems
                                02-133Urs Kanus, Gregor Wetekam, Johannes Hirche, Michael MeißnerVIZARD II: An FPGA-based Interactive Volume Rendering System
                                02-134Tony StansfieldWordlength as an Architectural Parameter for Reconfigurable Computing Devices
                                02-135João M. P. Cardoso, Markus WeinhardtXPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture

                              • eecejk
                                2004 paper list 04-1 João Canas Ferreira, José Silva Matos A Development Support System for Applications That Use Dynamically Reconfigurable Hardware 04-2
                                Message 15 of 26 , Feb 9, 2015
                                  2004 paper list

                                  04-1João Canas Ferreira, José Silva MatosA Development Support System for Applications That Use Dynamically Reconfigurable Hardware
                                  04-2Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim TuanA Dual-VDD Low Power FPGA Architecture
                                  04-3Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen TeichA Dynamic NoC Approach for Communication in Reconfigurable Devices
                                  04-4Xin Jia, Jayanthi Rajagopalan, Ranga VemuriA Dynamically Reconfigurable Asynchronous FPGA Architecture
                                  04-5Sumit Mohanty, Viktor K. PrasannaA Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems
                                  04-6Minoru Watanabe, Fuminori KobayashiA High-Density Optically Reconfigurable Gate Array Using Dynamic Method
                                  04-7Daniel Denning, James Irvine, Malachy DevlinA Key Agile 17.4 Gbit/sec Camellia Implementation
                                  04-8Jonathan Graf, Peter M. AthanasA Key Management Architecture for Securing Off-Chip Data Transfers
                                  04-9Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel MozosA Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management
                                  04-10Erik Schüler, Luigi CarroA Low Power FPAA for Wide Band Applications
                                  04-11Jingzhao Ou, Viktor K. PrasannaA Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
                                  04-12David V. Schuehler, John W. LockwoodA Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
                                  04-13Oliver A. Pfänder, Roland Hacker, Hans-Jörg PfleidererA Multiplexer-Based Concept for Reconfigurable Multiplier Arrays
                                  04-14Joseph Palmer, Brent E. NelsonA Parallel FFT Architecture for FPGAs
                                  04-15María Dolores Valdés, Miguel A. Domínguez, María José Moure, Camilo QuintánsA Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses
                                  04-16Christophe Layer, Hans-Jörg PfleidererA Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data
                                  04-17Herbert Walder, Marco PlatznerA Runtime Environment for Reconfigurable Hardware Operating Systems
                                  04-18Christos-Savvas Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. BharathA Steerable Complex Wavelet Construction and Its Implementation on FPGA
                                  04-19N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne LukA Structured Methodology for System-on-an-FPGA Design
                                  04-20Changchun Shi, James Hwang, Scott McMillan, Ann Root, Vinay SinghA System Level Resource Estimation Tool for FPGAs
                                  04-21Norbert Pramstaller, Johannes WolkerstorferA Universal and Efficient AES Co-processor for Field Programmable Logic Arrays
                                  04-22Tim Kerins, Emanuel M. Popovici, William P. MarnaneAlgorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes
                                  04-23Jawad Khan, Ranga VemuriAn Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms
                                  04-24Ricardo S. Ferreira, João M. P. Cardoso, Horácio C. NetoAn Environment for Exploring Data-Driven Architectures
                                  04-25Jim TorresenAn Evolvable Hardware Tutorial
                                  04-26Muhammad Atif Tahir, Ahmed Bouridane, Fatih KurugolluAn FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer
                                  04-27Shin'ichi Wakabayashi, Kenji KikuchiAn Instance-Specific Hardware Algorithm for Finding a Maximum Clique
                                  04-28Manish Handa, Ranga VemuriAn Integrated Online Scheduling and Placement Methodology
                                  04-29Renqiu Huang, Manish Handa, Ranga VemuriAnalysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs
                                  04-30Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio GarcíaArea*Time Optimized Hogenauer Channelizer Design Using FPL Devices
                                  04-31Edson L. Horta, John W. LockwoodAutomated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
                                  04-32Mark Holland, Scott HauckAutomatic Creation of Reconfigurable PALs/PLAs for SoC
                                  04-33Zachary K. Baker, Viktor K. PrasannaAutomatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
                                  04-34Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne LukAutomating Optimized Table-with-Polynomial Function Evaluation for FPGAs
                                  04-35Shawn Phillips, Akshay Sharma, Scott HauckAutomating the Layout of Reconfigurable Subsystems via Template Reduction
                                  04-36Nicola Campregher, Peter Y. K. Cheung, Milan VasilkoBIST Based Interconnect Fault Location for FPGAs
                                  04-37Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Fabio Campi, Mario TomaCompact Buffered Routing Architecture
                                  04-38Gustavo Sutter, Gery Bioul, Jean-Pierre DeschampsComparative Study of SRT-Dividers in FPGA
                                  04-39A. Bigot, F. Charpentier, Helena Krupnova, I. SansDeploying Hardware Platforms for SoC Validation: An Industrial Case Study
                                  04-40Faycal Bensaali, Abbes AmiraDesign and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic
                                  04-41Cesar Torres-Huitzil, René Cumplido-Parra, Santos López-EstradaDesign and Implementation of a CFAR Processor for Target Detection
                                  04-42Rawat SiripokarpiromDistribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs
                                  04-43Chun Te Ewe, Peter Y. K. Cheung, George A. ConstantinidesDual Fixed-Point: An Efficient Alternative to Floating-Point Computation
                                  04-44Alexander Thomas, Jürgen BeckerDynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures
                                  04-45Miljan Vuletic, Laura Pozzi, Paolo IenneDynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
                                  04-46Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques QuisquaterEfficient Modular Division Implementation: ECC over GF(p) Affine Coordinates Application
                                  04-47Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle TammemäeEvaluating Fault Emulation on FPGA
                                  04-48Didier Keymeulen, Ricardo Salem Zebulum, Adrian Stoica, Vu Duong, Michael I. FergusonEvolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device
                                  04-49Joseph Zambreno, David Nguyen, Alok N. ChoudharyExploring Area/Delay Tradeoffs in an AES FPGA Implementation
                                  04-50Cristinel Ababei, Pongstorn Maidee, Kia BazarganExploring Potential Benefits of 3D FPGA Integration
                                  04-51Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel CamozzatoFiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
                                  04-52Tom Van Court, Yongfeng Gu, Martin C. HerbordtFPGA Acceleration of Rigid Molecule Interactions
                                  04-53Marcos Martínez Peiró, Francisco Ballester, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. BelenguerFPGA Custom DSP for ECG Signal Analysis and Compression
                                  04-54Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge WeberFPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T
                                  04-55Quoc Thai Ho, Daniel MassicotteFPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems
                                  04-56Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis EntrenaFPGA Implementation of Biometric Authentication System Based on Hand Geometry
                                  04-57Ireneusz Janiszewski, Hermann Meuth, Bernhard HoppeFPGA-Efficient Hybrid LUT/CORDIC Architecture
                                  04-58Wim RoelandtsFPGAs and the Era of Field Programmability
                                  04-59Abilio Parreira, João Paulo Teixeira, Marcelino B. SantosFPGAs BIST Evaluation
                                  04-60Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher W. V. HogueHardware Accelerated Novel Protein Identification
                                  04-61Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa RiesgoHardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion
                                  04-62Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de LimaHardware Design of a FPGA-Based Synchronizer for Hiperlan/2
                                  04-63Björn Griese, Erik Vonnahme, Mario Porrmann, Ulrich RückertHardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures
                                  04-64Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Joel ArraisHardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers
                                  04-65Viktor Fischer, Milos Drutarovský, Martin Simka, Nathalie BochardHigh Performance True Random Number Generator in Altera Stratix FPLDs
                                  04-66Jesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos CuadradoHigh Throughput Serpent Encryption Implementation
                                  04-67Holger Lange, Andreas KochHW/SW Co-design by Automatic Embedding of Complex IP Cores
                                  04-68Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-GhazawiImplementation of Elliptic Curve Cryptosystems over GF(2n) in Optimal Normal Basis on a Reconfigurable Computer
                                  04-69Takehiro Ito, Yuichiro Shibata, Kiyoshi OguriImplementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA
                                  04-70Eduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agulló, Atilà Herms-BerenguerImplementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA
                                  04-71Michael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul SainiImproving FPGA Performance and Area Using an Adaptive Logic Module
                                  04-72Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. SpallekIncreasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration
                                  04-73Claudiu Zissulescu, Bart Kienhuis, Ed F. DeprettereIncreasing Pipelined IP Core Utilization in Process Networks Using Exploration
                                  04-74Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. GuptaInterconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures
                                  04-75Frederick C. Furtek, Eugene Hogenauer, James ScheuermannInterconnecting Heterogeneous Nodes in an Adaptive Computing Machine
                                  04-76Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai LeongIP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter
                                  04-77Martin SchoeberlJava Technology in an FPGA
                                  04-78Alexandra Poetter, Jesse Hunter, Cameron D. Patterson, Peter M. Athanas, Brent E. Nelson, Neil SteinerJHDLBits: The Merging of Two Worlds
                                  04-79Stefan Dydel, Piotr BalaLarge Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices
                                  04-80Fatih Kocan, Jason MeyerLogic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays
                                  04-81Hossam A. ElGindy, George FerizisMapping Basic Recursive Structures to Runtime Reconfigurable Hardware
                                  04-82Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. GoutisMapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path
                                  04-83Tim Todman, Wayne LukMethods and Tools for High-Resolution Imaging
                                  04-84Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio BenavidesMinimum Sum of Absolute Differences Implementation in a Single FPGA Device
                                  04-85Maya Gokhale, Janette Frigo, Christine Ahrens, Justin L. Tripp, Ronald MinnichMonte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer
                                  04-86Nalin Sidahao, George A. Constantinides, Peter Y. K. CheungMultiple Restricted Multiplication
                                  04-87Philip James-Roxby, Gordon J. BrebnerMultithreading in a Hyper-programmable Platform for Networked Systems
                                  04-88Andrei Bartic, Dirk Desmet, Jean-Yves Mignolet, Théodore Marescaux, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, J. Miller, Frédéric RobertNetwork-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation
                                  04-89Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping LiuOn Optimal Irregular Switch Box Designs
                                  04-90Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen BeckerOn-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities
                                  04-91Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der VeenOptimal Routing-Conscious Dynamic Placement for Reconfigurable Devices
                                  04-92Andrzej KrasniewskiOptimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory
                                  04-93Alexander Danilin, Sergei SawitzkiOptimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs
                                  04-94Yutaka Sugawara, Mary Inaba, Kei HirakiOver 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems
                                  04-95Brandon Blodget, Christophe Bobda, Michael Hübner, Adronis NiyonkuruPartial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs
                                  04-96François-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart PreneelPower Analysis Attacks Against FPGA Implementations of the DES
                                  04-97Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis EntrenaPower Consumption Reduction Through Dynamic Reconfiguration
                                  04-98Rajarshi Mukherjee, Seda Ogrenci MemikPower-Driven Design Partitioning
                                  04-99Gordon J. BrebnerProgrammable Logic Has More Computational Power than Fixed Logic
                                  04-100Javier Díaz, Eduardo Ros, Sonia Mota, Richard R. Carrillo, Rodrigo AgísReal Time Optical Flow Processing System
                                  04-101Tsutomu MaruyamaReal-Time Computation of the Generalized Hough Transform
                                  04-102Sandeep S. Kumar, Christof PaarReconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor
                                  04-103Nick Tredennick, Brion ShimamotoReconfigurable Systems Emerge
                                  04-104Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul ChengRun-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
                                  04-105Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen BeckerScalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems
                                  04-106Jérémie Detrey, Florent de DinechinSecond Order Function Approximation Using a Single Multiplication on FPGAs
                                  04-107Kris Tiri, Ingrid VerbauwhedeSecure Logic Synthesis
                                  04-108Unai Bidarte, Armando Astarloa, José Luis Martín, Jon AndreuSimulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design
                                  04-109Gang Chen, Jason CongSimultaneous Timing Driven Clustering and Placement for FPGAs
                                  04-110Arthur Segard, François VerdierSOC and RTOS: Managing IPs and Tasks Communications
                                  04-111Tero Rissa, Peter Y. K. Cheung, Wayne LukSoftSONIC: A Customisable Modular Platform for Video Applications
                                  04-112C. J. Tavares, C. Bungardean, G. M. Matos, José T. de SousaSolving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor
                                  04-113Masato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu AmanoStochastic Simulation for Biochemical Reactions on FPGA
                                  04-114Dalia Dagher, Iyad OuaissStorage Allocation for Diverse FPGA Memory Specifications
                                  04-115Mark DickinsonSystem-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?
                                  04-116Yang Qu, Kari Tiensyrjä, Kostas MasselosSystem-Level Modeling of Dynamically Reconfigurable Co-processors
                                  04-117Adam Donlin, Axel Braun, Adam RoseSystemC for the Design and Modeling of Programmable Systems
                                  04-118Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu SuzukiTechniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases
                                  04-119Chrilly Donninger, Ulf LorenzThe Chess Monster Hydra
                                  04-120Steven J. E. Wilton, Su-Shin Ang, Wayne LukThe Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
                                  04-121Jonathan Noel Tombs, Miguel Angel Aguirre Echánove, Fernando Muñoz Chavero, Vicente Baena Lecuyer, Antonio Jesús Torralba Silgado, A. Fernandez-León, Francisco TortosaThe Implementation of a FPGA Hardware Debugger System with Minimal System Overhead
                                  04-122Sebastian Lange, Martin MiddendorfThe Partition into Hypercontexts Problem for Hyperreconfigurable Architectures
                                  04-123Elena Moscu Panainte, Koen Bertels, Stamatis VassiliadisThe PowerPC Backend Molen Compiler
                                  04-124Mihail Petrov, Tudor Murgan, Frank May, Martin Vorbach, Peter Zipf, Manfred GlesnerThe XPP Architecture and Its Co-simulation Within the Simulink Environment
                                  04-125Yoshiki Yamaguchi, Tsutomu Maruyama, Akihiko KonagayaThree-Dimensional Dynamic Programming for Homology Search
                                  04-126Marcos R. Boschetti, Sergio Bampi, Ivan Saraiva SilvaThroughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters
                                  04-127Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias MüllerUsing of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment
                                  04-128Hagen Gädke, Andreas KochWavelet-Based Image Compression on the Reconfigurable Computer ACE-V

                                • eecejk
                                  2005 paper list 05-1 Chao You, Jong-Ru Guo, Michael Chu, Russell P. Kraft, Bryan S. Goda, John F. McDonald A 11 GHz FPGA with Test Applications 05-2 John
                                  Message 16 of 26 , Feb 9, 2015
                                    2005 paper list

                                    05-1Chao You, Jong-Ru Guo, Michael Chu, Russell P. Kraft, Bryan S. Goda, John F. McDonaldA 11 GHz FPGA with Test Applications
                                    05-2John Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Wang Jiang ChauA Dynamically Reconfigurable Bluetooth Base Band Unit
                                    05-3Clint Hilton, Brent E. NelsonA Flexible Circuit-Switched NOC for FPGA-Based Systems
                                    05-4Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred GlesnerA Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata
                                    05-5Victor Gonçalves, José T. de Sousa, Fernando M. GonçalvesA Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits
                                    05-6Xin Jia, Ranga VemuriA Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation
                                    05-7Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko Hännikäinen, Timo D. HämäläinenA Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC
                                    05-8Laurent Fesquet, Marc RenaudinA Programmable Logic Architecture for Prototyping Clockless Circuits
                                    05-9Zhiguo Ge, Hock-Beng Lim, Weng-Fai WongA Reconfigurable Instruction Memory Hierarchy for Embedded Systems
                                    05-10Peter Jamieson, Jonathan RoseA Verilog RTL Synthesis Tool for Heterogeneous FPGAs
                                    05-11Yongfeng Gu, Tom Van Court, Martin C. HerbordtAccelerating Molecular Dynamics Simulations With Configurable Circuits
                                    05-12Najeem Lawal, Benny Thörnberg, Mattias O'NilsAddress Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems
                                    05-13Alastair M. Smith, George A. Constantinides, Peter Y. K. CheungAn Analytical Approach to Generation and Exploration of Reconfigurable Architectures
                                    05-14Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-ArrontesAn Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation
                                    05-15Pedro Domingos, Fernando M. Silva, Horácio C. NetoAn Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning
                                    05-16Qiang Qiang, Daniel G. Saab, Jacob A. AbrahamAn Emulation Model for Sequential ATPG-Based Bounded Model Checking
                                    05-17Dusan Suvakovic, Ilija HadzicAn FPGA Application with High Speed Serial Transceiver Running at Sub-nominal Rate
                                    05-18Kenji Kanazawa, Tsutomu MaruyamaAn FPGA Solver for WSAT Algorithms
                                    05-19Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt KeutzerAn FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding
                                    05-20Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei HasegawaAn I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration?
                                    05-21Hisashi Tsukiashi, Masahiro Iida, Toshinori SueyoshiApplying the Small-World Network to Routing Structure of FPGAs
                                    05-22Akshay Sharma, Carl Ebeling, Scott HauckArchitecture-Adaptive Routability-Driven Placement for FPGAs
                                    05-23Mark Holland, Scott HauckAutomatic Creation of Domain-Specific Reconfigurable CPLDs for SoC
                                    05-24Sherif Yusuf, Wayne LukBitwise Optimised CAM for Network Intrusion Detection Systems
                                    05-25Miyoshi Saito, Hisanori Fujisawa, Nobuo Ujiie, Hideki YoshizawaCluster Architecture for Reconfigurable Signal Processing Engine for Wireless Communication
                                    05-26Claudiu Zissulescu, Bart Kienhuis, Ed F. DeprettereCommunication Synthesis in a multiprocessor environment
                                    05-27Henry Styles, Wayne LukCompilation and Management of Phase-Optimized Reconfigurable Systems
                                    05-28Michael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge WeberConfigurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis
                                    05-29Marc Bautista-Palacios, Luis Baldez, Jordi Sempere-Agulló, Atilà Herms-Berenguer, Francisco Cardells-Tormo, Pep-Lluis MolinetConfigurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGA
                                    05-30Nico Kasprzyk, Jan van der Veen, Andreas KochConfiguration Merging for Adaptive Computer Applications
                                    05-31Heiko Kalte, Mario PorrmannContext Saving and Restoring for Multitasking in Reconfigurable Systems
                                    05-32Robert G. Dimond, Oskar Mencer, Wayne LukCUSTARD - A Customisable Threaded FPGA Soft Processor and Tools
                                    05-33Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng MeiCustom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes
                                    05-34Zohair Hyder, John WawrzynekDefect Tolerance in Multiple-FPGA Systems
                                    05-35Anthony J. Yu, Guy G. LemieuxDefect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
                                    05-36Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der VeenDyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices
                                    05-37Pascal T. Wolkotte, Gerard J. M. Smit, Jens E. BeckerEnergy-Efficient NoC for Best-Effort Communication
                                    05-38Chun Te Ewe, Peter Y. K. Cheung, George A. ConstantinidesError Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic
                                    05-39Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel, Urs Kanus, Wolfgang StraßerEvaluation of Ray Casting on Processor-Like Reconfigurable Architectures
                                    05-40Chi-Wei Wang, Nicholas P. Carter, Richard B. Kujoth, Jeffrey J. Cook, Derek B. GottliebExploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor
                                    05-41Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. NandyFast FPGA Placement using Space-filling Curve
                                    05-42Heikki Kariniemi, Jari NurmiFault-Tolerant XGFT Network-On-Chip for Multi-Processor System-on-Chip Circuits
                                    05-43Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. HartensteinFELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations
                                    05-44Andrew C. Ling, Deshanand P. Singh, Stephen Dean BrownFPGA PLB Evaluation using Quantified Boolean Satisfiability
                                    05-45Iosifina Pournara, Christos-Savvas Bouganis, George A. ConstantinidesFPGA-Accelerated Reconstruction of Gene Regulatory Networks
                                    05-46Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo PimentelFPGA-based implementation and comparison of recursive and iterative algorithms
                                    05-47Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc RenaudinGALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips
                                    05-48Vincent Carlier, Hervé Chabanne, Emmanuelle Dottax, Hervé PelletierGeneralizing Square Attack using Side-Channels of an AES Implementation on an FPGA
                                    05-49Charles M. Kastner, G. Adam Covington, Andrew A. Levine, John W. LockwoodHAIL: A Hardware-Accelerated Algorithm for Language Identification
                                    05-50Giorgos Papadopoulos, Dionisios N. PnevmatikatosHashing + Memory = Low Cost, Exact Pattern Matching
                                    05-51Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. ConstantinidesHeterogeneity Exploration for Multiple 2D Filter Designs
                                    05-52I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. AndersonHierarchical Placement for Large-scale FPAA
                                    05-53Javier Díaz, Eduardo Ros, Sonia Mota, Eva M. Ortigosa, Begoña del PinoHigh Performance Stereo Computation Architecture
                                    05-54Shrutisagar Chandrasekaran, Abbes AmiraHigh Speed / Low Power Architectures for the Finite Radon Transform
                                    05-55Yutaka Sugawara, Mary Inaba, Kei HirakiHigh-speed and Memory Efficient TCP Stream Scanning using FPGA
                                    05-56Seppo Virtanen, Dragos Truscan, Jani Paakkulainen, Jouni Isoaho, Johan LiliusHighly Automated FPGA Synthesis of Application-Specific Protocol Processors
                                    05-57Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale CorsonelloLow-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor
                                    05-58Andy Gean Ye, Jonathan RoseMeasuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks
                                    05-59Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. VissersMemory Efficient Design of an MPEG-4 Video Encoder for FPGAs
                                    05-60Michael B. Healy, Mongkol Ekpanyapong, Sung Kyu LimMILP-based Placement and Routing for Dataflow Architecture
                                    05-61N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick LysaghtModular Partial Reconfiguration in Virtex FPGAs
                                    05-62Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko KonagayaMultidimensional Dynamic Programming for Homology Search
                                    05-63Todd S. Sproull, Gordon J. Brebner, Christopher E. NeelyMutable Codesign for Embedded Protocol Processing
                                    05-64Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne LukNovel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing
                                    05-65Olivier Héron, Talal Arnaout, Hans-Joachim WunderlichOn the Reliability Evaluation of SRAM-Based FPGA Designs
                                    05-66Sujan Pandey, Manfred Glesner, Max MühlhäuserOn-Chip Communication Topology Synthesis for a Shared Memory Architecture
                                    05-67Tsuyoshi Hamada, Naohito NakasatoPGR: A Software Package for Reconfigurable Super-Computing
                                    05-68Valavan Manohararajah, Deshanand P. Singh, Stephen Dean BrownPost-Placement BDD-Based Decomposition for FPGAs
                                    05-69Nalin Sidahao, George A. Constantinides, Peter Y. K. CheungPower and Area Optimization for Multiple Restricted Multiplication
                                    05-70Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred GlesnerProgrammable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata
                                    05-71Tsutomu Sasao, Shinobu Nagayama, Jon T. ButlerProgrammable Numerical Function Generators: Architectures and Synthesis Method
                                    05-72David Nguyen, Gokhan Memik, Seda Ogrenci Memik, Alok N. ChoudharyReal-Time Feature Extraction for High Speed Networks
                                    05-73Hiroaki Niitsuma, Tsutomu MaruyamaReal-time Generation of Three-Dimensional Motion Fields
                                    05-74Marek Gorgon, Slawomir Cichon, Miroslaw PacReal-time Handel-C Based Implementation of DV Decoder
                                    05-75Haoyu Song, Todd S. Sproull, Michael Attig, John W. LockwoodSnort Offloader: A Reconfigurable Hardware NIDS Filter
                                    05-76Wenhai Fang, Thomas Johansson, Lambert SpaanenburgSnow 2.0 IP Core for Trusted Hardware
                                    05-77Shankar Balachandran, Dinesh BhatiaTiming Aware Interconnect Prediction Models for FPGAs
                                    05-78Sebastien C. Wong, Mark Jasiunas, David A. KearneyTowards a Reconfigurable Tracking System
                                    05-79Justin L. Tripp, Kristopher D. Peterson, Christine Ahrens, Jeffrey D. Poznanovic, Maya GokhaleTrident: An FPGA Compiler Framework for Floating-Point Algorithms
                                    05-80Gareth W. Morris, George A. Constantinides, Peter Y. K. CheungUsing DSP Blocks For ROM Replacement: A Novel Synthesis Flow
                                    05-81Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan VasilkoYield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes
                                    05-82Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne LukZiggurat-based Hardware Gaussian Random Number Generator
                                  • eecejk
                                    2006 paper list 06-1 Peter Alfke 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications 06-2 Hideharu Amano, Yohei Hasegawa, Shohei Abe,
                                    Message 17 of 26 , Feb 9, 2015
                                      2006 paper list

                                      06-1Peter Alfke65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications
                                      06-2Hideharu Amano, Yohei Hasegawa, Shohei Abe, Kenichiro Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi NishimuraA Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors
                                      06-3Boris Kettelhoit, Mario PorrmannA Layer Model for Systematically Designing Dynamically Reconfigurable Systems
                                      06-4Andrea Lodi, Claudio Mucci, Massimo Bocchi, Andrea Cappelli, Mario de Dominicis, Luca CiccarelliA Multi-Context Pipelined Array for Embedded Systems
                                      06-5Alastair M. Smith, George A. Constantinides, Peter Y. K. CheungA Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
                                      06-6Imran Ahmed, Tughrul ArslanA Reconfigurable Viterbi Decoder for a Communication Platform
                                      06-7Allen Michalski, Duncan A. BuellA Scalable Architecture for RSA Cryptography on Large FPGAs
                                      06-8Wenyin Fu, Katherine ComptonA Simulation Platform for Reconfigurable Computing Research
                                      06-9Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul ChowA System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification
                                      06-10Phillip H. Jones, John W. Lockwood, Young H. ChoA Thermal Management and Profiling Method for Reconfigurable Hardware Applications
                                      06-11Ian PageAcademia to IPO - A Modern Odyssey
                                      06-12Julien Lamoureux, Steven J. E. WiltonActivity Estimation for Field-Programmable Gate Arrays
                                      06-13Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. SotiriouActual-Delay Circuits on FPGA: Trading-Off Luts for Speed
                                      06-14Valavan Manohararajah, Stephen Dean Brown, Zvonko G. VranesicAdaptive FPGAs: High-Level Architecture and a Synthesis Method
                                      06-15Luis F. Rodriguez-Ramos, Angel Alonso, Fernando Gago, Jose V. Gigante, Guillermo Herrera, Teodora VieraAdaptive Optics Real-Time Control Using FPGA
                                      06-16Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu AmanoAn FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems
                                      06-17Takashi Saegusa, Tsutomu MaruyamaAn FPGA Implementation of K-Means Clustering for Color Images Based on Kd-Tree
                                      06-18Kenji Kanazawa, Tsutomu MaruyamaAn FPGA Solver for Large SAT Problems
                                      06-19C. K. Wong, Philip Heng Wai LeongAn FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic
                                      06-20Tom Van Court, Martin C. HerbordtApplication-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
                                      06-21Thilo Pionteck, Roman Koch, Carsten AlbrechtApplying Partial Reconfiguration to Networks-On-Chips
                                      06-22Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott HemmertArchitectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs
                                      06-23Florian Stock, Andreas KochArchitecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays
                                      06-24Andreas Fidjeland, Wayne LukArchlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming
                                      06-25Zhi Guo, Abhishek Mitra, Walid A. NajjarAutomation of IP Core Interface Generation for Reconfigurable Computing
                                      06-26Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, Oliver PellComparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
                                      06-27Oliver Pell, Wayne LukCompiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information
                                      06-28Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader BagherzadehConfiguration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures
                                      06-29Konstantinos Masselos, George A. Constantinides, Qiang LiuData Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm
                                      06-30Pongstorn Maidee, Kia BazarganDefect-Tolerant FPGA Architecture Exploration
                                      06-31Fernando J. Álvarez, Álvaro Hernández, Jesús Ureña, Juan Jesús García, Ana Jiménez, P. Santa TeresaDetection Module in a Complementary Set of Sequences-Based Pulse Compression System
                                      06-32Hristo Nikolov, Todor Stefanov, Ed F. DeprettereEfficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips
                                      06-33Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne LukEfficient Realtime FPGA Implementation of the Trace Transform
                                      06-34Sujan Pandey, Manfred GlesnerEnergy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture
                                      06-35Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan BridgfordEnhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs
                                      06-36Pengyuan Yu, Patrick SchaumontExecuting Hardware as Parallel Software for Picoblaze Networks
                                      06-37Klaus Danne, Roland Mühlenbernd, Marco PlatznerExecuting Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions
                                      06-38David de Andrés, Juan Carlos Ruiz, Daniel Gil, Pedro J. GilFast Emulation of Permanent Faults in VLSI Systems
                                      06-39Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro NakamuraFault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells
                                      06-40Mike HuttonFPGA Architecture Design Methodology
                                      06-41Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai LeongFPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach
                                      06-42Luis G. Barbero, John S. ThompsonFPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems
                                      06-43Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu SusinFPGA Design of A H.264/AVC Main Profile Decoder for HDTV
                                      06-44Mariano Lopez Garcia, Enrique F. Cantó-NavarroFPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor
                                      06-45Lerong Cheng, Jinjun Xiong, Lei He, Mike HuttonFPGA Performance Optimization Via Chipwise Placement Considering Process Variations
                                      06-46Dries Schellekens, Bart Preneel, Ingrid VerbauwhedeFPGA Vendor Agnostic True Random Number Generator
                                      06-47Christos-Savvas Bouganis, Peter Y. K. Cheung, Zhaoping LiFPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex
                                      06-48Nele Mentens, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede, Bart PreneelFpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor
                                      06-49Ken McElvainFPGAs at 65NM and Beyond - Powerful New FPGAs Bring New Challenges
                                      06-50Owen Callanan, David Gregg, Andy Nisbet, Mike PeardonHigh Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD
                                      06-51G. Adam Covington, Charles L. G. Comstock, Andrew A. Levine, John W. Lockwood, Young H. ChoHigh Speed Document Clustering in Reconfigurable Hardware
                                      06-52Ling Zhuo, Viktor K. PrasannaHigh-Performance and Parameterized Matrix Factorization on FPGAs
                                      06-53Daniel Ziener, Stefan Assmus, Jürgen TeichIdentifying FPGA IP-Cores Based on Lookup Table Content Analysis
                                      06-54Dang Ba Khac Trieu, Tsutomu MaruyamaImplementation of a Parallel and Pipelined Watershed Algorithm on FPGA
                                      06-55Yongfeng Gu, Tom Van Court, Martin C. HerbordtImproved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations
                                      06-56Hayden Kwok-Hay So, Robert W. BrodersenImproving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support
                                      06-57Keith Gowan, Jason Nery, Henrick Han, Tony Sheng, Howard Li, Fakhreddine Karray, Insop SongIntelligent Parking System Design Using FPGA
                                      06-58Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-BäseIPP Watermarking Technique for IP Core Protection on FPL Devices
                                      06-59George Ferizis, Hossam A. ElGindyMapping Recursive Functions to Reconfigurable Hardware
                                      06-60Nastaran Baradaran, Pedro C. DinizMemory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures
                                      06-61Chidamber Kulkarni, Gordon J. BrebnerMicro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor
                                      06-62Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen TeichMinimizing Communication Cost for Reconfigurable Slot Modules
                                      06-63Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry P. BorerModular Partitioning for Incremental Compilation
                                      06-64Michael T. Frederick, Arun K. SomaniMulti-Bit Carry Chains for High-Performance Reconfigurable Fabrics
                                      06-65Love Singhal, Elaheh BozorgzadehMulti-layer Floorplanning on a Sequence of Reconfigurable Designs
                                      06-66Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred GlesnerMultitasking Support for Dynamically Reconfig Urable Systems
                                      06-67David B. Thomas, Wayne LukNon-Uniform Random Number Generation Through Piecewise Linear Approximations
                                      06-68Guillermo Marcus Martinez, Gerhard Lienhart, Andreas Kugel, Reinhard MännerOn Buffer Management Strategies for High Performance Computing with Reconfigurable Hardware
                                      06-69Goncalo M. de Matos, Horácio C. NetoOn Reconfigurable Architectures for Efficient Matrix Inversion
                                      06-70Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne LukOn-FPGA Communication Architectures and Design Factors
                                      06-71Janina A. Brenner, Jan van der Veen, Sándor P. Fekete, Julio A. de Oliveira Filho, Wolfgang RosenstielOptimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures
                                      06-72Andreas Schallenberg, Wolfgang Nebel, Frank OppenheimerOSSS+R: Modelling and Simulating Self-Reconfigurable Systems
                                      06-73Jan Torben Weinkopf, Klaus Harbich, Erich BarkeParsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models
                                      06-74Pao-Ann Hsiung, Chun-Hsian Huang, Chih-Feng LiaoPerfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable Systems
                                      06-75Mike Hutton, Yan Lin, Lei HePlacement and Timing for FPGAs Considering Variations
                                      06-76Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. WiltonPower Implications of Implementing Logic Using FPGA Embedded Memory Arrays
                                      06-77Michael Gilroy, James IrvineRAID 6 Hardware Acceleration
                                      06-78David J. Lau, Orion PritchardRapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions
                                      06-79Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Ken-ichi Suzuki, Tadao Nakamura, Nobuyuki OhbaRay Tracing Hardware System Using Plane-Sphere Intersections
                                      06-80Jean-Baptiste Note, Mark Shand, Jean VuilleminReal-Time Video Pixel Matching
                                      06-81Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan VasilkoReconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs
                                      06-82Allan Carroll, Carl EbelingReducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
                                      06-83Zachary K. Baker, Viktor K. Prasanna, Hong-Jip JungRegular Expression Software Deceleration for Intrusion Detection Systems
                                      06-84Ari Kulmala, Timo D. Hämäläinen, Marko HännikäinenReliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA
                                      06-85K. S. Tham, Douglas L. MaskellSoftware-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor
                                      06-86Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López AlcantudSynthesis on FPAA of a Smart Sthetoscope Analog Subsystem
                                      06-87Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko PettissaloSystem Level Architecture Exploration for Reconfigurable Systems On Chip
                                      06-88Usama Malik, Oliver DiesselThe Entropy of FPGA Reconfiguration
                                      06-89Manuel Saldaña, Paul ChowTMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
                                      06-90Dionisios N. Pnevmatikatos, Aggelos ArelakisVariable-Length Hashing for Exact Pattern Matching
                                      06-91Oswaldo Cadenas, Graham M. MegsonVerification and FPGA Circuits of a Block-2 Fast Path-Based Predictor

                                    • eecejk
                                      2007 paper list 07-1 Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann A Design Methodology for Communication Infrastructures on Partially
                                      Message 18 of 26 , Feb 9, 2015
                                        2007 paper list

                                        07-1Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario PorrmannA Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs
                                        07-2Pongstorn Maidee, Kia BazarganA generalized and unified SPFD-based rewiring technique
                                        07-3Shuichi Watanabe, Junji Kitamichi, Kenichi KurodaA Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem
                                        07-4Heiner Giefers, Marco PlatznerA Many-core Implementation based on the Reconfigurable Mesh Model
                                        07-5Karel Bruneel, Peter Bertels, Dirk StroobandtA Method for Fast Hardware Specialization at run-time
                                        07-6Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. NollA Power Estimation Model for an FPGA-based Softcore Processor
                                        07-7Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Bart KincaidA Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA
                                        07-8Graham Schelle, Jeff Fifield, Dirk GrunwaldA Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects
                                        07-9Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu AmanoA Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems
                                        07-10Martin SchoeberlA Time-Triggered Network-on-Chip
                                        07-11Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, Satish MummareddyA Unified Streaming Architecture for Real Time Face Detection and Gender Classification
                                        07-12Jahyun J. Koo, Alan C. Evans, Warren J. GrossAccelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer
                                        07-13Phillip H. Jones, James Moscola, Young H. Cho, John W. LockwoodAdaptive Thermoregulation for Applications on Reconfigurable Devices
                                        07-14John WawrzynekAdventures with a Reconfigurable Research Platform
                                        07-15Zdenek Vasícek, Lukás SekaninaAn area-efficient alternative to adaptive median filtering in FPGAs
                                        07-16Michael Wisdom, Peter LeeAn Efficient Implementation of a 2D DWT on FPGA
                                        07-17Holger Lange, Andreas KochAn Execution Model for Hardware/Software Compilation and its System-Level Realization
                                        07-18Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. LeeAn FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
                                        07-19Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis PsarrisApplying Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems
                                        07-20Johan Ditmar, Steve McKeeverArray Synthesis in SystemC Hardware Compilation
                                        07-21Christian Schuck, Stefan Lamparth, Jürgen BeckerartNoC - A Novel Multi-Functional Router Architecture for Organic Computing
                                        07-22Esam El-Araby, Ivan Gonzalez, Tarek A. El-GhazawiBringing High-Performance Reconfigurable Computing to Exact Computations
                                        07-23Julien Lamoureux, Steven J. E. WiltonClock-Aware Placement for FPGAs
                                        07-24Gareth W. Morris, Matthew AuburyDesign Space Exploration of the European Option Benchmark Using HyperStreams
                                        07-25Josh Model, Martin C. HerbordtDiscrete Event Simulation of Molecular Dynamics with Configurable Logic
                                        07-26Pan Yu, Tulika MitraDisjoint Pattern Enumeration for Custom Instructions Identification
                                        07-27Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. WiltonDomain-Specific Hybrid FPGA: Architecture and Floating Point Applications
                                        07-28John Shield, Peter Sutton, Philip MachanickDynamic Cache Switching in Reconfigurable Embedded Systems
                                        07-29Jamshid Shokrollahi, Elisa Gorla, Christoph PuttmannEfficient FPGA-based multipliers for F_3^97 and F_3^(6*97)
                                        07-30Yang Liu, Christos-Savvas Bouganis, Peter Y. K. CheungEfficient mapping of a Kalman filter into an FPGA using Taylor Expansion
                                        07-31Bradley R. Quinton, Steven J. E. WiltonEmbedded Programmable Logic Core Enhancements for System Bus Interfaces
                                        07-32Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara TharmalingamEquivalence Verification of FPGA and Structured ASIC Implementations
                                        07-33Pao-Ann Hsiung, Chih-Wen LiuExploiting Hardware and Software Low Power Techniques for Energy Efficient Co-scheduling in Dynamically Reconfigurable Systems
                                        07-34Chee Sing Lee, Wei Ting Loke, Wenjuan Zhang, Yajun HaFast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools
                                        07-35Xuegong Zhou, Ying Wang, XunZhang Huang, Chenglian PengFast On-line Task Placement and Scheduling on Reconfigurable Devices
                                        07-36Michael Crocker, Michael T. Niemier, Xiaobo Sharon HuFault Models and Yield Analysis for QCA-based PLAs
                                        07-37Jérémie Detrey, Florent de DinechinFloating-Point Trigonometric Functions for FPGAs
                                        07-38Aric D. Blumer, Henning S. Mortveit, Cameron D. PattersonFormal Modeling of Process Migration
                                        07-39Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu AmanoFPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method
                                        07-40Octavian Cret, Zsolt Mathe, Paul Ciobanu, Sonia Marginean, Cristian LelutiuGENDIV - A Hardware Algorithm for Intron and Exon String Detection in DNA Chains
                                        07-41Adam Major, Ioannis Nousias, Sami Khawam, Mark Milward, Ying Yi, Mark Muir, Tughrul ArslanH.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture
                                        07-42Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis VassiliadisHARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation
                                        07-43Yoshiki Yamaguchi, Tsutomu Maruyama, Fumikazu Konishi, Akihiko KonagayaHigh speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequences
                                        07-44Katarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, Jürgen BeckerImplementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs
                                        07-45Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene, Doris T. ChenImproving Annealing Via Directed Moves
                                        07-46Hendrik Eeckhaut, Mark Christiaens, Dirk StroobandtImproving External Memory Access for Avalon Systems on Programmable Chips
                                        07-47Martin Labrecque, J. Gregory SteffanImproving Pipelined Soft Processors with Multithreading
                                        07-48Doris T. Chen, Kristofer Vorwerk, Andrew A. KenningsImproving Timing-Driven FPGA Packing With Physical Information
                                        07-49Encarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-RuízIntellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting
                                        07-50John A. Nestor, Jeremy LavineL4: An FPGA-Based Accelerator for Detailed Maze Routing
                                        07-51Rashad S. Oreifej, Rawad N. Al-Haddad, Heng Tan, Ronald F. DeMaraLayered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices
                                        07-52Shannon Koh, Oliver DiesselModule Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
                                        07-53Panagiotis D. Vouzis, Sylvain Collange, Mark G. Arnold, Mayuresh V. KothareMonte Carlo Logarithmic Number System for Model Predictive Control
                                        07-54Florian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen BeckerMORPHEUS: Heterogeneous Reconfigurable Computing
                                        07-55Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk CorporaalMulti-processor System-level Synthesis for Multiple Applications on Platform FPGA
                                        07-56Jonathan A. Clarke, George A. Constantinides, Peter Y. K. CheungOn the feasibility of early routing capacitance estimation for FPGAs
                                        07-57Katarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian GamratOn-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project
                                        07-58S. Murtaza, Alfons G. Hoekstra, Peter M. A. SlootPerformance Modeling of 2D Cellular Automata on FPGA
                                        07-59Jorge Guajardo, Sandeep S. Kumar, Geert Jan Schrijen, Pim TuylsPhysical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection
                                        07-60Juanjo Noguera, Irwin O. KennedyPower Reduction in Network Equipment through Adaptive Partial Reconfiguration
                                        07-61Shilpa Bhoj, Dinesh BhatiaPre-route Interconnect Capacitance and Power Estimation in FPGAs
                                        07-62Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves DrozRAMP Blue: A Message-Passing Manycore System in FPGAs
                                        07-63Enno Lübbers, Marco PlatznerReconOS: An RTOS supporting Hard- and Software Threads
                                        07-64Steve TrimbergerRedefining the FPGA for the Next Generation
                                        07-65Mário P. Véstias, Horácio C. NetoRouter Design for Application Specific Networks-on-Chip on Reconfigurable Systems
                                        07-66Fernando Pardo, P. López, Diego CabelloSoft-Hard 3D FD-TD Solver for Non Destructive Evaluation
                                        07-67Satish Sivaswamy, Kia BazarganStatistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs
                                        07-68Erik K. Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David L. AndrewsSupporting High Level Language Semantics Within Hardware Resident Threads
                                        07-69Mark DickinsonSystem-Level Design for FPGAs
                                        07-70Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai SunTANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms
                                        07-71Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, Florian Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, Marcos MartínezThe ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems
                                        07-72Wei Han, Ioannis Nousias, Mark Muir, Tughrul Arslan, Ahmet T. ErdoganThe Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures
                                        07-73Ajay V. BhattThe Intel Geneseo Project
                                        07-74Christof Pitter, Martin SchoeberlTime Predictable CPU and DMA Shared Memory Access
                                        07-75Mahim Mishra, Seth Copen GoldsteinVirtualization on the Tartan Reconfigurable Architecture

                                      • eecejk
                                        2008 paper list 08-1 Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich A comparison of embedded reconfigurable
                                        Message 19 of 26 , Feb 9, 2015
                                          2008 paper list

                                          08-1Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen TeichA comparison of embedded reconfigurable video-processing architectures
                                          08-2Lars Bauer, Muhammad Shafique, Jörg HenkelA computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor
                                          08-3Jose Luis Nunez-Yanez, Eddie Hung, Vassilios A. ChouliarasA configurable and programmable motion estimation processor for the H.264 video codec
                                          08-4Claudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari NurmiA dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck
                                          08-5Shilpa Bhoj, Dinesh BhatiaA dynamic temperature control simulation system for FPGAs
                                          08-6Tobias KrawutschkeA flexible and reliable embedded system for detector control in a high energy physics experiment
                                          08-7Markus Koester, Wayne Luk, Geoffrey BrownA hardware compilation flow for instance-specific VLIW cores
                                          08-8Andreas Ehliar, Per Karlström, Dake LiuA high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA
                                          08-9Andre Guntoro, Manfred GlesnerA lifting-based DWT and IDWT processor with multi-context configuration and normalization factor
                                          08-10Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro KoibuchiA link removal methodology for Networks-on-Chip on reconfigurable systems
                                          08-11Fujie Wong, Yajun HaA low overhead fault tolerant FPGA with new connection box
                                          08-12Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen BeckerA multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput
                                          08-13Christian Hochberger, Alexander WeissA new methodology for debugging and validation of soft cores
                                          08-14Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham HassouneA non-volatile run-time FPGA using thermally assisted switching MRAMS
                                          08-15Enno Lübbers, Marco PlatznerA portable abstraction layer for hardware threads
                                          08-16Panagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytraki, Dionisios N. PnevmatikatosA rate-based prefiltering approach to blast acceleration
                                          08-17Michail Zampetakis, Vasilis Samoladas, Apostolos DollasA reconfigurable accelerator for quantum computations
                                          08-18Theepan Moorthy, Andy YeA scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays
                                          08-19Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-Chung Hsu, Arun Kundu, Andrew A. KenningsA technique for minimizing power during FPGA placement
                                          08-20Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi OnoderaA variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS
                                          08-21Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del CampoA versatile hardware architecture for a CFAR detector based on a linear insertion sorter
                                          08-22Bharat Sukhwani, Martin C. HerbordtAcceleration of a production rigid molecule docking code
                                          08-23Wenyin Fu, Katherine ComptonActive kernel monitoring to combat scheduler gaming in reconfigurable computing systems
                                          08-24Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne LukAn analytical model describing the relationships between logic architecture and FPGA density
                                          08-25Hanyu Liu, Xiaolei Chen, Yajun HaAn architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects
                                          08-26Jorge Surís, Cameron D. Patterson, Peter AthanasAn efficient run-time router for connecting modules in FPGAS
                                          08-27Jing Hu, Steven F. Quigley, Andrew ChanAn element-by-element preconditioned Conjugate Gradient solver of 3D tetrahedral finite elements on an FPGA coprocessor
                                          08-28Kimon Karras, Elias S. ManolakosAn embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture
                                          08-29Séamas McGettrick, Dermot Geraghty, Ciarán McElroyAn FPGA architecture for the Pagerank eigenvector problem
                                          08-30Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker LindenstruthAn FPGA-based high-speed, low-latency trigger processor for high-energy physics
                                          08-31David Boland, George A. ConstantinidesAn FPGA-based implementation of the MINRES algorithm
                                          08-32Jason Wu, John W. Williams, Neil W. BergmannAn ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC
                                          08-33Kevin Camera, Robert W. BrodersenAn integrated debugging environment for FPGA computing platforms
                                          08-34Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. BuellAn optimization method of DMA transfer for a general purpose reconfigurable machine
                                          08-35Stanislaw Deniziak, Mariusz WisniewskiAn symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation
                                          08-36Young-Su Kwon, Bontae Koo, Nak-Woong EumApplication-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor
                                          08-37Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. NollApplication-specific reconfigurable processors
                                          08-38George Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine LeligouArchitecture and implementation of a Frame Aggregation Unit for optical frame-based switching
                                          08-39Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank HannigArea and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures
                                          08-40Gang Zhou, Li Li, Harald MichalikArea optimization of bit parallel finite field multipliers with fast carry logic on FPGAS
                                          08-41Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe HoogvorstArea optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic
                                          08-42Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel JantschATCA-based computation platform for data acquisition and triggering in particle physics experiments
                                          08-43Karel Bruneel, Dirk StroobandtAutomatic generation of run-time parameterizable configurations
                                          08-44Radu Andrei Stefan, Sorin Dan CotofanaBitstream compression techniques for Virtex 4 FPGAs
                                          08-45Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji TodaBitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems
                                          08-46Ralf Joost, Ralf SalomonBOUNCE, a new approach to measure sub-nanosecond time intervals
                                          08-47Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. EggersCHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures
                                          08-48Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi SatohChosen-message SPA attacks against FPGA-based RSA hardware implementations
                                          08-49César Pedraza, Emilio Castillo, Javier Castillo, Cristobal Camarero, José Luis Bosque, José Ignacio Martínez, Rafael Menéndez de LlanoCluster architecture based on low cost reconfigurable hardware
                                          08-50Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-JimenezCoarse-grain dynamically reconfigurable coprocessor for image processing in SOPC
                                          08-51Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred GlesnerCoarse-grained reconfiguration
                                          08-52Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. CheungCombining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework
                                          08-53Kevin K. Liu, Charles B. Cameron, Antal A. SarkadyComparing throughput and power consumption in both sequential and reconfigurable processors
                                          08-54Jason R. Villarreal, Walid A. NajjarCompiled hardware acceleration of Molecular Dynamics code
                                          08-55Betul Buyukkurt, Walid A. NajjarCompiler generated systolic arrays for wavefront algorithm acceleration on FPGAs
                                          08-56Donald G. Bailey, Christopher T. Johnston, Ni MaConnected components analysis of streamed images
                                          08-57Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel TorresConvergence analysis of run-time distributed optimization on adaptive systems using game theory
                                          08-58James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. BenningtonCreating unique identifiers on field programmable gate arrays using natural processing variations
                                          08-59Hongbing Fan, Jason Ernst, Yu-Liang WuCustomized Reconfigurable Interconnection Networks for multiple application SOCS
                                          08-60Yasuhiro Ito, Yutaka Sugawara, Mary Inaba, Kei HirakiCVC: The C to RTL compiler for callback-based verification model
                                          08-61Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen BeckerData path driven waveform-like reconfiguration
                                          08-62Horácio C. Neto, Mário P. VéstiasDecimal multiplier on FPGA using embedded binary multipliers
                                          08-63Haiting Tian, Shakith Fernando, Hock Wei Soon, Yajun Ha, Nanguang ChenDesign of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA
                                          08-64Martin Kumm, M. Shahab SanjariDigital hilbert transformers for FPGA-based phase-locked loops
                                          08-65Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang NgDirect sigma-delta modulated signal processing in FPGA
                                          08-66Markos Papadonikolakis, Christos-Savvas BouganisEfficient FPGA mapping of Gilbert's algorithm for SVM training on large-scale classification problems
                                          08-67Oliver A. Pfänder, Hans-Jörg PfleidererEMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs
                                          08-68Diego P. Morales, Antonio García, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitan-VallveyEnhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration
                                          08-69Tim Güneysu, Christof Paar, Gerd Pfeiffer, Manfred SchimmlerEnhancing COPACOBANA for advanced applications in cryptography and cryptanalysis
                                          08-70Viktor Fischer, Florent Bernard, Nathalie Bochard, Michal VarcholaEnhancing security of ring oscillator-based trng implemented in FPGA
                                          08-71Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-YáñezEvaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor
                                          08-72Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo HironakaExploring compact design on high throughput coarse grained reconfigurable architectures
                                          08-73Graham Schelle, Dirk GrunwaldExploring FPGA network on chip implementations across various application and network loads
                                          08-74Paul Schumacher, Pradip JhaFast and accurate resource estimation of RTL-based designs targeting FPGAS
                                          08-75Tomasz S. Czajkowski, Stephen Dean BrownFast toggle rate computation for FPGA circuits
                                          08-76Edward A. Stott, N. Pete Sedcole, Peter Y. K. CheungFault tolerant methods for reliability in FPGAs
                                          08-77Hayden Kwok-Hay So, Robert W. BrodersenFile system access from reconfigurable FPGA hardware processes in BORPH
                                          08-78Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate MerkerFine grain reconfigurable architectures
                                          08-79Martin LanghammerFloating point datapath synthesis for FPGAs
                                          08-80Alexander Kaganov, Paul Chow, Asif LakhanyFPGA acceleration of Monte-Carlo based credit derivative pricing
                                          08-81Nathan A. Woods, Tom VanCourtFPGA acceleration of quasi-Monte Carlo in finance
                                          08-82Pongstorn Maidee, Nagib Hakim, Kia BazarganFPGA family composition and effects of specialized blocks
                                          08-83Christiane Beuschel, Hans-Jörg PfleidererFPGA implementation of a flexible decoder for long LDPC codes
                                          08-84Haile Yu, Yuk Hei Chan, Philip Heng Wai LeongFPGA interconnect design using logical effort
                                          08-85Ivo BolsensFPGA: The future platform for transforming, transporting and computing data
                                          08-86L. MusaFPGAS in high energy physics experiments at CERN
                                          08-87Miguel Lino Silva, João Canas FerreiraGeneration of partial FPGA configurations at run-time
                                          08-88Tamas Malek, Tomás Martínek, Jan KorenekGICS: Generic interconnection system
                                          08-89Andre Guntoro, Manfred GlesnerHigh-performance fpga-based floating-point adder with three inputs
                                          08-90Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi KamiyaHigh-speed regular expression matching engine using multi-character NFA
                                          08-91Takashi Saegusa, Tsutomu Maruyama, Yoshiki YamaguchiHow fast is an FPGA in image processing?
                                          08-92Sebastian Lange, Martin MiddendorfHyperreconfigurable architectures
                                          08-93Ahmad Sghaier, Shawki Areibi, Robert D. DonyIEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration
                                          08-94Martin Danek, Jiri Kadlec, Roman Bartosinski, Lukas KohoutIncreasing the level of abstraction in FPGA-based designs
                                          08-95Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu AmanoInstruction buffer mode for multi-context Dynamically Reconfigurable Processors
                                          08-96Syed Waqar Nabi, Cade C. Wells, Wim VanderbauwhedeInterface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor
                                          08-97O. WohlmuthKeynote: High performance computing based on FPGAS
                                          08-98Meikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean ShaLoop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory
                                          08-99Ozana Silvia Dragomir, Todor Stefanov, Koen BertelsLoop unrolling and shifting for reconfigurable architectures
                                          08-100Holger Lange, Andreas KochLow-latency high-bandwidth HW/SW communication in a virtual memory environment
                                          08-101Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong HongMacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation
                                          08-102Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai LeongMapping and scheduling with task clustering for heterogeneous computing systems
                                          08-103Hagen Gädke, Florian Stock, Andreas KochMemory access parallelisation in high-level language compilation for reconfigurable adaptive computers
                                          08-104Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones, Brian S. Martin, Ryan FongMetawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
                                          08-105Song Sun, Joseph ZambrenoMining Association Rules with systolic trees
                                          08-106Spyridon Ninos, Apostolos DollasModeling recursion data structures for FPGA-based implementation
                                          08-107Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas HerkersdorfNetwork processors
                                          08-108Diana Göhringer, Michael Hübner, Thomas Perschke, Jürgen BeckerNew dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach
                                          08-109Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen TeichNo-break dynamic defragmentation of reconfigurable devices
                                          08-110Henrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana Gadelha Serra dos SantosNOC architecture design for multi-cluster chips
                                          08-111Changjian Gao, Shih-Lien LuNovel FPGA based Haar classifier face detection algorithm acceleration
                                          08-112Shinobu Nagayama, Tsutomu Sasao, Jon T. ButlerNumerical function generators using bilinear interpolation
                                          08-113Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik MaehleOn the design parameters of runtime reconfigurable systems
                                          08-114Ricardo Chaves, Georgi Kuzmanov, Leonel SousaOn-the-fly attestation of reconfigurable hardware
                                          08-115Marco D. Santambrogio, Vincenzo Rana, Donatella SciutoOperating system support for online partial dynamic reconfiguration management
                                          08-116Norbert Abel, Frederik Grüll, Nick Meier, Andreas Beyer, Udo KebschullParallel hardware objects for dynamically partial reconfiguration
                                          08-117Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi OnoderaPerformance optimization by track swapping on critical paths utilizing random variations for FPGAS
                                          08-118Amit Pande, Joseph ZambrenoPolymorphic wavelet architectures using reconfigurable hardware
                                          08-119Stephen McKeown, Roger Woods, John McAllisterPower efficient DSP datapath configuration methodology for FPGA
                                          08-120Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu AmanoPower reduction techniques for Dynamically Reconfigurable Processor Arrays
                                          08-121Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu AmanoPractical implementation of a network-based stochastic biochemical simulation system on an FPGA
                                          08-122Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. WiltonRapid estimation of power consumption for hybrid FPGAs
                                          08-123Oliver Bowen, Christos-Savvas BouganisReal-time image super resolution using an FPGA
                                          08-124Dirk Koch, Christian Beckhoff, Jürgen TeichReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS
                                          08-125Alexander Danilin, Sergei Sawitzki, Erik RijshouwerReconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems
                                          08-126Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien PicardReconfigurable hardware: The holy grail of matching performance with programming productivity
                                          08-127Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dudek, Thomas Dowrick, Liam McDaidReconfigurable platforms and the challenges for large-scale implementations of spiking neural networks
                                          08-128Ricardo S. Ferreira, Marcone Laure, Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi CarroReducing interconnection cost in coarse-grained dynamic computing through multistage network
                                          08-129Vlad Mihai Sima, Elena Moscu Panainte, Koen BertelsResource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform
                                          08-130David B. Thomas, Wayne LukSampling from the exponential distribution using independent Bernoulli variates
                                          08-131Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro ShirakiSAT-based resource binding for reducing critical path delays
                                          08-132Eoin Creedon, Michael ManzkeScalable high performance computing on FPGA clusters using message passing
                                          08-133Hoang Le, Weirong Jiang, Viktor K. PrasannaScalable high-throughput SRAM-based architecture for IP-lookup using FPGA
                                          08-134Andreas Schallenberg, Achim Rettberg, Wolfgang Nebel, Franz-Josef RammigSeamless design flow for reconfigurable systems
                                          08-135Dan WerthimerSearching for ET with FPGA'S
                                          08-136Benoît Badrignans, Reouven Elbaz, Lionel TorresSecure FPGA configuration architecture preventing system downgrade
                                          08-137Enrique Cantó, Francesc Fons, Mariano LópezSelf-recofigurable embedded systems on Spartan-3
                                          08-138Mamoun F. Al-MistarihiSeparable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA
                                          08-139Shakith Fernando, Xiaolei Chen, Yajun HasFPGA - A scalable switch based FPGA architecture and design methodology
                                          08-140Matthew A. Watkins, Mark J. Cianchetti, David H. AlbonesiShared reconfigurable architectures for CMPS
                                          08-141Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron SassTeaching FPGA system design via a remote laboratory facility
                                          08-142Ping Chen, Andy YeThe effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays
                                          08-143Immacolata Colacicco, Giacomo Marchiori, Raffaele TripiccioneThe hardware application platform of the hartes project
                                          08-144Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru OyanagiThree-stage pipeline implementation for SHA2 using data forwarding
                                          08-145Brian Leung, Yan Pan, Christopher L. Schroeder, Seda Ogrenci Memik, Gokhan Memik, Mitra J. Z. HartmannTowards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system
                                          08-146Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero RissaTowards benchmarking energy efficiency of reconfigurable architectures

                                        • eecejk
                                          2009 paper list 09-1 Yiwei Zhang, José L. Núñez-Yáñez, Joe McGeehan, Edward Regan, Stephen Kelly A biophysically accurate floating point somatic
                                          Message 20 of 26 , Feb 9, 2015
                                            2009 paper list

                                            09-1Yiwei Zhang, José L. Núñez-Yáñez, Joe McGeehan, Edward Regan, Stephen KellyA biophysically accurate floating point somatic neuroprocessor
                                            09-2Roberto Selow, Heitor S. Lopes, Carlos R. Erig LimaA comparison of FPGA and FPAA technologies for a signal processing application
                                            09-3Joannis Sotiropoulos, Ioannis PapaefstathiouA fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems
                                            09-4Sang Kyun Kim, Lawrence C. McAfee, Peter Leonard McMahon, Kunle OlukotunA highly scalable Restricted Boltzmann Machine FPGA implementation
                                            09-5Daniel Le Ly, Paul ChowA multi-FPGA architecture for stochastic Restricted Boltzmann Machines
                                            09-6Slavisa Jovanovic, Camel Tanougast, Serge Weber, Christophe BobdaA new deadlock-free fault-tolerant routing algorithm for NoC interconnections
                                            09-7Konstantinos Kyriakoulakos, Dionisios N. PnevmatikatosA novel SRAM-based FPGA architecture for efficient TMR fault tolerance support
                                            09-8Dong Wang, Milos D. Ercegovac, Nanning ZhengA radix-8 complex divider for FPGA implementation
                                            09-9Marco D. Santambrogio, Massimo Morandi, Marco Novati, Donatella SciutoA runtime relocation based workflow for self dynamic reconfigurable systems design
                                            09-10Trevor Spiteri, George Vafiadis, Jose Luis Nunez-YanezA toolset for the analysis and optimization of motion estimation algorithms and processors
                                            09-11Toyokazu Takagi, Tsutomu MaruyamaAccelerating HMMER search using FPGA
                                            09-12Enrique Cantó, Mariano Fons, Mariano López-Farcía, Rafael Ramos-LaraAcceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3
                                            09-13Tobias Schumacher, Christian Plessl, Marco PlatznerAn accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
                                            09-14Scott Y. L. Chin, Steven J. E. WiltonAn analytical model relating FPGA architecture and place and route runtime
                                            09-15Andreas Ehliar, Dake LiuAn ASIC perspective on FPGA optimizations
                                            09-16Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred GlesnerAn integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs
                                            09-17Alastair M. Smith, George A. Constantinides, Peter Y. K. CheungArea estimation and optimisation of FPGA routing fabrics
                                            09-18Carles Nicolau, Dolors Sala, Enrique CantóClock duplicity for high-precision timestamping in Gigabit Ethernet
                                            09-19Safeen Huda, Muntasir Mallick, Jason Helge AndersonClock gating architectures for FPGA power reduction
                                            09-20Clément Farabet, Cyril Poulet, Jefferson Y. Han, Yann LeCunCNP: An FPGA-based processor for Convolutional Networks
                                            09-21Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao OnoyeCoarse-grained dynamically reconfigurable architecture with flexible reliability
                                            09-22Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed CurtisComparing fine-grained performance on the Ambric MPPA against an FPGA
                                            09-23Mojtaba Sabeghi, Vlad Mihai Sima, Koen BertelsCompiler assisted runtime task scheduling on a reconfigurable computer
                                            09-24Jason CongCustomizable domain-specific computing
                                            09-25Peter Yiannacouras, J. Gregory Steffan, Jonathan RoseData parallel FPGA workloads: Software versus hardware
                                            09-26Heiko Hinkelmann, Peter Zipf, Manfred GlesnerDesign and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes
                                            09-27Dimitrios Kontos, Ioannis Papaefstathiou, Dionisios N. PnevmatikatosDesign space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths
                                            09-28Rajesh Velegalati, Jens-Peter KapsDPA resistance for light-weight implementations of cryptographic algorithms on FPGAs
                                            09-29Matt Chiu, Martin C. HerbordtEfficient particle-pair filtering for acceleration of molecular dynamics simulation
                                            09-30Franjo Plavec, Zvonko G. Vranesic, Stephen Dean BrownEnhancements to FPGA design methodology using streaming
                                            09-31Hadi Parandeh-Afshar, Philip Brisk, Paolo IenneExploiting fast carry-chains of FPGAs for designing compressor trees
                                            09-32Qiwei Jin, David B. Thomas, Wayne LukExploring reconfigurable architectures for explicit finite difference option pricing models
                                            09-33Martin Labrecque, J. Gregory SteffanFast critical sections via thread scheduling for FPGA-based multithreaded processors
                                            09-34Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo XuFPGA accelerating three QR decomposition algorithms in the unified pipelined framework
                                            09-35Vaughn BetzFPGA challenges and opportunities at 40nm and beyond
                                            09-36Jonathan Heiner, Benjamin Sellers, Michael J. Wirthlin, Jeff KalbFPGA partial reconfiguration via configuration scrubbing
                                            09-37Wim Vanderbauwhede, Leif Azzopardi, Mahmoud MoadeliFPGA-accelerated Information Retrieval: High-efficiency document filtering
                                            09-38Josef Angermeier, Abdulazim Amouri, Jürgen TeichGeneral methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems
                                            09-39Florent de Dinechin, Cristian Klein, Bogdan PascaGenerating high-performance custom floating-point pipelines
                                            09-40Masato Inagi, Yasuhiro Takashima, Yuichi NakamuraGlobally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA system
                                            09-41Shanyuan Gao, Andrew G. Schmidt, Ron SassHardware implementation of MPI_Barrier on an FPGA cluster
                                            09-42Florent Camarda, Jean-Christophe Prévotet, Fabienne NouvelImplementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcasting
                                            09-43Jason Helge Anderson, Qiang WangImproving logic density through synthesis-inspired architecture
                                            09-44Bita Nezamfar, Mark HorowitzIn field, energy-performance tunable FPGA architectures
                                            09-45Peter AthanasIn search of agile hardware
                                            09-46Hiren J. Patel, Yong C. Kim, J. Todd McDonald, LaVern A. StarmanIncreasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysis
                                            09-47Krzysztof Kepa, Fearghal Morgan, Krzysztof KosciuszkiewiczIP protection in Partially Reconfigurable FPGAs
                                            09-48Florent de Dinechin, Bogdan PascaLarge multipliers with fewer DSP blocks
                                            09-49Caglar Kalaycioglu, Onur Can Ulusel, Ilker HamzaogluLow power techniques for Motion Estimation hardware
                                            09-50Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne LukModeling post-techmapping and post-clustering FPGA circuit depth
                                            09-51Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu AmanoMuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link
                                            09-52Brian H. Pratt, Michael J. Wirthlin, Michael P. Caffrey, Paul S. Graham, Keith MorganNoise impact of single-event upsets on an FPGA-based digital filter
                                            09-53Arpith C. Jacob, Jeremy D. Buhler, Roger D. ChamberlainOptimal runtime reconfiguration strategies for systolic arrays
                                            09-54Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. ConstantinidesOptimising designs by combining model-based and pattern-based transformations
                                            09-55Christopher Claus, Robert Huitl, Joachim Rausch, Walter StecheleOptimizing the SUSAN corner detection algorithm for a high speed FPGA implementation
                                            09-56Shuichi Asano, Tsutomu Maruyama, Yoshiki YamaguchiPerformance comparison of FPGA, GPU and CPU in image processing
                                            09-57Nachiket Kapre, André DeHonPerformance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
                                            09-58Tomasz Kryjak, Marek GorgonPipeline implementation of the 128-bit block cipher CLEFIA in FPGA
                                            09-59Heiner Giefers, Marco PlatznerProgram-driven fine-grained power management for the reconfigurable mesh
                                            09-60Kentaro Kokufuta, Tsutomu MaruyamaReal-time processing of local contrast enhancement on FPGA
                                            09-61Adam Jacobs, Alan D. George, Grzegorz CieslewskiReconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space
                                            09-62Iouliia Skliarova, Valery SklyarovRecursion in reconfigurable computing: A survey of implementation approaches
                                            09-63David Leong, Guy G. LemieuxReplace: An incremental placement algorithm for field programmable gate arrays
                                            09-64Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen TeichSelf-organizing multi-cue fusion for FPGA-based embedded imaging
                                            09-65Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj VeeravallisFPGA2 - A scalable GALS FPGA architecture and design methodology
                                            09-66Diana Göhringer, Bin Liu, Michael Hübner, Jürgen BeckerStar-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol
                                            09-67Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, Scott HauckStatic versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
                                            09-68Jonathan RoseThe evolution of architecture exploration of programmable devices
                                            09-69Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter ZipfTowards a unique FPGA-based identification circuit using process variations
                                            09-70Kaveh Aasaraai, Andreas MoshovosTowards a viable out-of-order soft core: Copy-Free, checkpointed register renaming
                                            09-71Peter AlfkeVirtex-6 and Spartan-6, plus a look into the future

                                          • eecejk
                                            2010 paper list 10-1 Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable
                                            Message 21 of 26 , Feb 9, 2015
                                              2010 paper list

                                              10-1Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk KochA Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs
                                              10-2Hagen Gädke-Lütjens, Benjamin Thielmann, Andreas KochA Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation
                                              10-3Wen-Hui Fu, Jun Jiang, Xi Qin, Ting Yi, Zhiliang HongA Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks
                                              10-4Philip Garcia, Kyle Rupnow, Katherine ComptonA Reconfigurable Computing Scheduler Optimized for Multicore Systems
                                              10-5Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang PoonA Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis
                                              10-6Francesco Bruschi, Marco Paolieri, Vincenzo RanaA Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching
                                              10-7Heiner Giefers, Marco PlatznerA Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier
                                              10-8Angel Quiros-Olozabal, Ma de los Angeles Cifredo Chacon, Jose Maria Guerrero-RodriguezAccurate Time-to-Digital Converter Based on Xilinx's Digital Clock Managers
                                              10-9Ye Lu, Sakir Sezer, John V. McCannyAdvanced Multithreading Architecture with Hardware Based Scheduling
                                              10-10Stefan Kirsch, Felix Rettig, Dirk Hutter, Jan de Cuveland, Venelin Angelov, Volker LindenstruthAn FPGA-based High-Speed, Low-Latency Processing System for High-Energy Physics
                                              10-11Malte Baesler, Sven-Ole Voigt, Thomas TeufelAn IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier
                                              10-12Brian Leung, Chih-Hung Wu, Seda Ogrenci Memik, Sanjay MehrotraAn Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs
                                              10-13Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. BrewsterATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs
                                              10-14Thilan Ganegedara, Yi-Hua E. Yang, Viktor K. PrasannaAutomation Framework for Large-Scale Regular Expression Matching on FPGA
                                              10-15Junfeng Fan, Daniel V. Bailey, Lejla Batina, Tim Güneysu, Christof Paar, Ingrid VerbauwhedeBreaking Elliptic Curve Cryptosystems Using Reconfigurable Hardware
                                              10-16Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori SueyoshiCOGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization
                                              10-17Otto Esko, Pekka Jääskeläinen, Pablo Huerta, Carlos S. de La Lama, Jarmo Takala, José Ignacio MartínezCustomized Exposed Datapath Soft-Core Design Flow with Compiler Support
                                              10-18Weirong Jiang, Viktor K. Prasanna, Norio YamagakiDecision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA
                                              10-19Shahrukh Athar, Muhammad Ali Siddiqi, Shahid MasudDesign and FPGA Implementation of a 2nd Order Adaptive Delta Sigma Modulator with One Bit Quantization
                                              10-20Martin Schoeberl, Peter HilberDesign and Implementation of Real-Time Transactional Memory
                                              10-21Maki Yasuda, Minoru WatanabeDynamically Reconfigurable Vision-Chip Architecture
                                              10-22Alessandro Cilardo, Paolo Durante, Carmelo Lofiego, Antonino MazzeoEarly Prediction of Hardware Complexity in HLL-to-HDL Translation
                                              10-23Gustavo Sutter, Jean-Pierre Deschamps, José Luis ImañaEfficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation
                                              10-24Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun KunduEfficient FPGA Resynthesis Using Precomputed LUT Structures
                                              10-25Thomas B. Preußer, Rainer G. SpallekEnhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains
                                              10-26Daniel W. Chang, Christipher D. Jenkins, Philip C. Garcia, Syed Zohaib Gilani, Paula Aguilera, Aishwarya Nagarajan, Michael J. Anderson, Matthew A. Kenny, Sean M. Bauer, Michael J. Schulte, Katherine ComptonERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing
                                              10-27Farnaz Gharibian, Lesley Shannon, Peter JamiesonFinding System-Level Information and Analyzing Its Correlation to FPGA Placement
                                              10-28Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori SueyoshiFirst Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
                                              10-29Christopher E. Neely, Gordon J. Brebner, Weijia ShangFlexible and Modular Support for Timing Functions in High Performance Networking Acceleration
                                              10-30Faisal Khan, Maya Gokhale, Chen-Nee ChuahFPGA Based Network Traffic Analysis Using Traffic Dispersion Patterns
                                              10-31Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Máire O'Neill, William P. MarnaneFPGA Implementations of the Round Two SHA-3 Candidates
                                              10-32Ricardo S. Ferreira, Julio C. Goldner VendraminiFPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks
                                              10-33David B. Thomas, Wayne LukFPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers
                                              10-34David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. CheungGPU Versus FPGA for High Productivity Computing
                                              10-35Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale MazoyerHigh Density Asynchronous LUT Based on Non-volatile MRAM Technology
                                              10-36Ralf Zimmermann, Tim Güneysu, Christof PaarHigh-Performance Integer Factoring with Reconfigurable Devices
                                              10-37Kostas Theocharoulis, Ioannis Papaefstathiou, Charalampos ManifavasImplementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking
                                              10-38Leandro Möller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, Manfred GlesnerImproving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers
                                              10-39Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent E. Nelson, Michael Rice, Michael J. WirthlinIncreasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
                                              10-40Lyonel Barthe, Pascal Benoit, Lionel TorresInvestigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures
                                              10-41Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott HauckManaging Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
                                              10-42Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. ConstantinidesMapping Multiple Multivariate Gaussian Random Number Generators on an FPGA
                                              10-43Nicolas Ngan, Geoffroy Marpeaux, Eva Dokladalova, Mohamed Akil, François Contou-CarrèreMemory System for a Dynamically Adaptable Pixel Stream Architecture
                                              10-44SangKyun Yun, KyuHee LeeOptimization of Regular Expression Pattern Matching Circuit Using At-Most Two-Hot Encoding on FPGA
                                              10-45Petr Matas, Eva Dokladalova, Mohamed Akil, Vjaceslav Georgiev, Martin PoupaParallel Hardware Implementation of Connected Component Tree Computation
                                              10-46Doris Chen, Deshanand P. SinghParallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs)
                                              10-47Florent de Dinechin, Hong Diep Nguyen, Bogdan PascaPipelined FPGA Adders
                                              10-48Dam Sunwoo, Gene Y. Wu, Nikhil A. Patil, Derek ChiouPrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems
                                              10-49Linfeng Ye, Jean-Philippe Diguet, Guy GogniatRapid Application Development on Multi-processor Reconfigurable Systems
                                              10-50Felipe Restrepo-Calle, Antonio Martínez-Álvarez, Francisco R. Palomo, Hipólito Guzmán-Miranda, M. A. Aguirre, Sergio Cuenca-AsensiRapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA
                                              10-51Weirong Jiang, Maya GokhaleReal-Time Classification of Multimedia Traffic Using FPGA
                                              10-52Michael Dreschmann, Michael Hübner, Moritz Roger, Oliver Sander, Christos Klamouris, Jürgen Becker, Wolfgang Freude, Juerg LeutholdReconfigurable Hardware for Power-over-Fiber Applications
                                              10-53Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves KrastevaRun-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs
                                              10-54Filippo Sironi, Marco Triverio, Henry Hoffmann, Martina Maggio, Marco D. SantambrogioSelf-Aware Adaptation in FPGA-based Systems
                                              10-55Kenneth M. Zick, John P. HayesSelf-Test and Adaptation for Random Variations in Reliability
                                              10-56Robin Panda, Jimmy Xu, Scott HauckSoftware Managed Distributed Memories in MPPAs
                                              10-57Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent RougeSurvey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs
                                              10-58Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Koichiro FurutaTest Compression for Dynamically Reconfigurable Processors
                                              10-59Sungmin Bae, Narayanan VijaykrishnanThermal Gradient Aware Clock Skew Scheduling for FPGAs
                                              10-60Vijay K. Sirigir, Khawla Alzoubi, Daniel G. Saab, Fatih Kocan, Massood Tabib-AzarUltra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA

                                            • eecejk
                                              2011 paper list 11-1 Hiroaki Inoue, Takashi Takenaka, Masato Motomura 20Gbps C-Based Complex Event Processing 11-2 Abdulazim Amouri, Mehdi Baradaran Tahoori A
                                              Message 22 of 26 , Feb 9, 2015
                                                2011 paper list

                                                11-1Hiroaki Inoue, Takashi Takenaka, Masato Motomura20Gbps C-Based Complex Event Processing 
                                                11-2Abdulazim Amouri, Mehdi Baradaran TahooriA Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAs
                                                11-3Harry Sidiropoulos, Kostas Siozios, Dimitrios SoudrisA Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
                                                11-4Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai LeongA Model for Matrix Multiplication Performance on FPGAs
                                                11-5Kashfia Haque, Paul BeckettA Radiation Hard Lut Block with Auto-Scrubbing
                                                11-6William V. Kritikos, Yamuna Rajasekhar, Andrew G. Schmidt, Ron SassA Radix Tree Router for Scalable FPGA Networks 
                                                11-7Xiang Tian, Christos-Savvas BouganisA Run-Time Adaptive FPGA Architecture for Monte Carlo Simulations 
                                                11-8Jason Cong, Muhuan Huang, Yi ZouAccelerating Fluid Registration Algorithm on Multi-FPGA Platforms 
                                                11-9Kenji Kanazawa, Tsutomu MaruyamaAn FPGA Solver for SAT-Encoded Formal Verification Problems 
                                                11-10Dang Ba Khac Trieu, Tsutomu MaruyamaAn Implementation of the Mean Shift Filter on FPGA
                                                11-11Cristiana Bolchini, Antonio Miele, Chiara SandionigiAutomated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems
                                                11-12Fatemeh Eslami, Mihai SimaCapacitive Boosting for FPGA Interconnection Networks
                                                11-13Oguzhan Erdem, Hoang Le, Viktor K. PrasannaClustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGA
                                                11-14Paulo Proenca, Ricardo ChavesCompact CLEFIA Implementation on FPGAS
                                                11-15Ismail San, Nuray AtCompact Hardware Architecture for Hummingbird Cryptographic Algorithm
                                                11-16Lubos Gaspar, Viktor Fischer, Lilian Bossuet, Milos DrutarovskýCryptographic Extension for Soft General-Purpose Processors with Secure Key Management
                                                11-17Joachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen BeckerEmbedded Systems Start-Up under Timing Constraints on Modern FPGAs 
                                                11-18Yong Cheol Peter Cho, Sungmin Bae, Yongseok Jin, Kevin M. Irick, Vijaykrishnan NarayananExploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA
                                                11-19Paul Schumacher, Pradip Jha, Sudha Kuntur, Tim Burke, Alan FrostFast RTL Power Estimation for FPGA Designs
                                                11-20Daniel Lo, Greg Malysa, G. Edward SuhFlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric
                                                11-21Nikolaos Alachiotis, Alexandros StamatakisFPGA Acceleration of the Phylogenetic Parsimony Kernel?
                                                11-22Will X. Y. Li, Rosa H. M. Chan, Wei Zhang, C. W. Yu, Ray C. C. Cheung, Dong Song, Theodore W. BergerFPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities 
                                                11-23Zhen Wang, Ding Xie, Jinmei LaiFPGA Interconnect Architecture Exploration Based on a Statistical Model
                                                11-24Hong Diep Nguyen, Bogdan Pasca, Thomas B. PreußerFPGA-Specific Arithmetic Optimizations of Short-Latency Adders
                                                11-25Ye Lu, John V. McCanny, Sakir SezerGeneric Low-Latency NoC Router Architecture for FPGA Computing Systems 
                                                11-26Yuanxi Peng, Manuel Saldaña, Paul ChowHardware Support for Broadcast and Reduce in MPSoC 
                                                11-27Michel A. Kinsy, Michael Pellauer, Srinivas DevadasHeracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
                                                11-28Christian Leber, Benjamin Geib, Heiner LitzHigh Frequency Trading Acceleration Using FPGAs
                                                11-29Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander SudnitsonImplementation in FPGA of Address-Based Data Sorting
                                                11-30Jocelyn Sérot, François Berry, Sameer AhmedImplementing Stream-Processing Applications on FPGAs: A DSL-Based Approach
                                                11-31Yousef Iskander, Cameron D. Patterson, Stephen D. CravenImproved Abstractions and Turnaround Time for FPGA Design Validation and Debug
                                                11-32Edward A. Stott, Peter Y. K. CheungImproving FPGA Reliability with Wear-Levelling
                                                11-33Rajesh Velegalati, Jens-Peter KapsImproving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs
                                                11-34Bill Teng, Jason Helge AndersonLatch-Based Performance Optimization for FPGAs 
                                                11-35Hadi Parandeh-Afshar, Paolo IenneMeasuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs
                                                11-36Rehan Ahmed, Peter HallschmidModeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks 
                                                11-37Grigorios Chrysos, Panagiotis Dagritzikos, Ioannis Papaefstathiou, Apostolos DollasNovel and Highly Efficient Reconfigurable Implementation of Data Mining Classification Tree
                                                11-38Haile Yu, Qiang Xu, Philip Heng Wai LeongOn Timing Yield Improvement for FPGA Designs Using Architectural Symmetry
                                                11-39Lyonel Barthe, Luis Vitório Cargnini, Pascal Benoit, Lionel TorresOptimizing an Open-Source Processor for FPGAs: A Case Study
                                                11-40Benjamin Thielmann, Jens Huthmann, Andreas KochPrecore - A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation
                                                11-41Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. HutchingsRapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs
                                                11-42Xinyu Niu, Kuen Hung Tsoi, Wayne LukReconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking
                                                11-43Marcel Gort, Jason Helge AndersonReducing FPGA Router Run-Time through Algorithm and Architecture
                                                11-44Mário P. Véstias, Horácio C. NetoRevisiting the Newton-Raphson Iterative Method for Decimal Division 
                                                11-45Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo Marrero Callicó, Roberto SarmientoRun-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs
                                                11-46Giorgos Dimitrakopoulos, Christoforos Kachris, Emmanouil KalligerosScalable Arbiters and Multiplexers for On-FPGA Interconnection Networks 
                                                11-47Daniel Llamocca, Cesar Carranza, Marios S. PattichisSeparable FIR Filtering in FPGA and GPU Implementations: Energy, Performance, and Accuracy Considerations
                                                11-48Seong-I. Lei, Wai-Kei MakSimultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign
                                                11-49Yuan Li, Paul Chow, Jiang Jiang, Minxuan ZhangSoftware/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method
                                                11-50Eddie Hung, Steven J. E. WiltonSpeculative Debug Insertion for FPGAs
                                                11-51Abhranil Maiti, Logan McDougall, Patrick SchaumontThe Impact of Aging on an FPGA-Based Physical Unclonable Function 
                                                11-52Mohammed M. Farag, Lee W. Lerner, Cameron D. PattersonThwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement
                                                11-53Xun Chen, Jianwen Zhu, Minxuan ZhangTiming-Driven Routing of High Fanout Nets
                                                11-54Thilan Ganegedara, Hoang Le, Viktor K. PrasannaTowards On-the-Fly Incremental Updates for Virtualized Routers on FPGA
                                                11-55Stefan Wildermann, Jürgen Teich, Daniel ZienerUnifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs
                                                11-56Yuanwu Lei, Yong Dou, Jie Zhou, Sufeng WangVPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic
                                                11-57Subhrashankha Ghosh, Brent E. NelsonXDL-Based Module Generators for Rapid FPGA Design Implementation 

                                              • eecejk
                                                2012 paper list 12-1 Takashi Yoza, Minoru Watanabe A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed
                                                Message 23 of 26 , Feb 9, 2015
                                                  2012 paper list

                                                  12-1Takashi Yoza, Minoru WatanabeA 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function
                                                  12-2Jason Xin Zheng, Ethan Chen, Miodrag PotkonjakA Benign Hardware Trojan on FPGA-based embedded systems
                                                  12-3Ashwin A. Mendon, Bin Huang, Ron SassA high performance, open source SATA2 core
                                                  12-4Abhranil Maiti, Patrick SchaumontA novel microprocessor-intrinsic Physical Unclonable Function
                                                  12-5Takashi Takenaka, Masamichi Takagi, Hiroaki InoueA scalable complex event processing framework for combination of SQL-based continuous queries and C/C++ functions
                                                  12-6Graeme Coapes, Terrence S. T. Mak, Junwen Luo, Alex Yakovlev, Chi-Sang PoonA scalable FPGA-based design for field programmable large-scale ion channel simulations
                                                  12-7Rinse Wester, Christiaan Baaij, Jan KuperA two step hardware design method using CλaSH
                                                  12-8Izaan Allugundu, Pranay Puranik, Yat Piu Lo, Akash KumarAcceleration of distance-to-default with hardware-software co-design
                                                  12-9Robin Panda, Carl Ebeling, Scott HauckAdding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array
                                                  12-10Daichi Kobori, Tsutomu MaruyamaAn acceleration of a graph cut segmentation with FPGA
                                                  12-11Chin Hau Hoo, Akash KumarAn area-efficient partially reconfigurable crossbar switch with low reconfiguration delay
                                                  12-12Wenjuan Deng, Yiqun Zhu, Hao Feng, Zhiguo JiangAn efficient hardware architecture of the optimised SIFT descriptor generation
                                                  12-13Haruhisa Tsuyama, Tsutomu MaruyamaAn FPGA acceleration of a level set segmentation method
                                                  12-14Marcel Gort, Jason Helge AndersonAnalytical placement for heterogeneous FPGAs
                                                  12-15Rodrigo Bernardo, Luis R. Monte, Eduardo Mobilon, Valentino Corso, Arley H. Salvador, Carolina G. Neves, Cleber A. Nakandakare, Daniele R. da Silva, Luis P. F. de Barros, Ronaldo F. da SilvaArchitecture and FPGA implementation of a 10.7 Gbit/s OTN Regenerator for optical communication systems
                                                  12-16Fatma Abouelella, Karel Bruneel, Dirk StroobandtAutomatically exploiting regularity in applications to reduce reconfiguration memory requirements
                                                  12-17Eugene Cartwright, Azad Fahkari, Sen Ma, Christina Smith, Miaoqing Huang, David L. Andrews, Jason AgronAutomating the design of mLUT MPSoPC FPGAs in the cloud
                                                  12-18Michael Henrey, Sean Edmond, Lesley Shannon, Carlo MenonBio-inspired walking: A FPGA multicore system for a legged robot
                                                  12-19Maria Kalenderi, Dionisios N. Pnevmatikatos, Ioannis Papaefstathiou, Charalampos ManifavasBreaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGAS
                                                  12-20Atabak Mahram, Martin C. HerbordtCAAD BLASTP 2.0: NCBI BLASTP accelerated with pipelined filters
                                                  12-21Björn Meyer, Jörn Schumacher, Christian Plessl, Jens FörstnerConvey vector personalities - FPGA acceleration with an openmp-like programming effort? 
                                                  12-22Bogdan PascaCorrectly rounded floating-point division for DSP-enabled FPGAs
                                                  12-23George Eichinger, Kaushik Chowdhury, Miriam LeeserCRUSH: Cognitive Radio Universal Software Hardware
                                                  12-24Raul Torrego, Inaki Val, Eñaut Muxika, Xabier Iturbe, Khaled BenkridData coding functions for Software Defined Radios implemented on R3TOS
                                                  12-25Michael J. Flynn, Oliver Pell, Oskar MencerDataflow supercomputing
                                                  12-26Keisuke Dohi, Yuma Hatanaka, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi OguriDeep-pipelined FPGA implementation of ellipse estimation for eye tracking
                                                  12-27Antoni Roca, José Flich, Giorgos DimitrakopoulosDESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS
                                                  12-28Adrien Le Masle, Wayne LukDetecting power attacks on reconfigurable hardware
                                                  12-29Daniel Llamocca, Cesar Carranza, Marios S. PattichisDynamic multiobjective optimization management of the Energy-Performance-Accuracy space for separable 2-D complex filters
                                                  12-30Adam Powell, Christos-Savvas Bouganis, Peter Y. K. CheungEarly performance estimation of image compression methods on soft processors
                                                  12-31Suvarna Mane, Mostafa M. I. Taha, Patrick SchaumontEfficient and side-channel-secure block cipher implementation with custom instructions on FPGA
                                                  12-32Michael Feilen, Matthias Ihmig, Christian Schwarzbauer, Walter StecheleEfficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources
                                                  12-33Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. KenningsEmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip
                                                  12-34Abid Rafique, Nachiket Kapre, George A. ConstantinidesEnhancing performance of Tall-Skinny QR factorization using FPGAs
                                                  12-35Xinyu Niu, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver PellExploiting run-time reconfiguration in stencil computation
                                                  12-36Zoltán Nagy, Csaba Nemes, Antal Hiba, András Kiss, Árpád Csík, Péter SzolgayFPGA based acceleration of computational fluid flow simulation on unstructured mesh geometry
                                                  12-37Swetha Pappala, Mohammed Y. Niamat, Weiqing SunFPGA based key generation technique for anti-counterfeiting methods using Physically Unclonable Functions and artificial intelligence
                                                  12-38Alexios Balatsoukas-Stimming, Apostolos DollasFPGA-based design and implementation of a multi-GBPS LDPC decoder
                                                  12-39Ken Eguro, Ramarathnam VenkatesanFPGAs for trusted cloud computing
                                                  12-40Thusitha N. Chandrapala, Amila P. Cabral, Sapumal Ahangama, Thilina S. Ambagahawaththa, Jayathu G. SamarawickramaHardware implementation of motion blur removal
                                                  12-41Jungwook Choi, Rob A. RutenbarHardware implementation of MRF map inference on an FPGA platform
                                                  12-42Yan Xu, Olivier Muller, Pierre-Henri Horrein, Frédéric PétrotHCM: An abstraction layer for seamless programming of DPR FPGA
                                                  12-43Abdulazim Amouri, Mehdi Baradaran TahooriHigh-level aging estimation for FPGA-mapped designs
                                                  12-44Andrew Somerville, Kenneth B. KentImproving memory support in the VTR flow
                                                  12-45Ghaith Tarawneh, Terrence S. T. Mak, Alex YakovlevIntra-chip physical parameter sensor for FPGAS using flip-flop metastability
                                                  12-46Thomas P. Perry, Richard L. Walke, Rob Payne, Stefan Petko, Khaled BenkridIP-XACT extensions for IP interoperability guarantees and software model generation
                                                  12-47Zhongduo Lin, Charles Lo, Paul ChowK-means implementation on FPGA for high-dimensional data using triangle inequality
                                                  12-48Eddie Hung, Steven J. E. WiltonLimitations of incremental signal-tracing for FPGA debug
                                                  12-49Karel Heyse, Karel Bruneel, Dirk StroobandtMapping logic to reconfigurable FPGA routing
                                                  12-50Elias Vansteenkiste, Karel Bruneel, Dirk StroobandtMaximizing the reuse of routing resources in a reconfiguration-aware connection router
                                                  12-51Aaron Wood, Adam Knight, Benjamin Ylvisaker, Scott HauckMulti-kernel floorplanning for enhanced CGRAS
                                                  12-52Yi-Chung Chen, Wenhua Wang, Hai Li, Wei ZhangNon-volatile 3D stacking RRAM-based FPGA
                                                  12-53Niyati Shah, Jonathan RoseOn the difficulty of pin-to-wire routing in FPGAs
                                                  12-54Qiwei Jin, Tobias Becker, Wayne Luk, David B. ThomasOptimising explicit finite difference option pricing for dynamic constant reconfiguration
                                                  12-55Thilan Ganegedara, Viktor K. Prasanna, Gordon J. BrebnerOptimizing packet lookup in time and space on FPGA
                                                  12-56Adam Jacobs, Grzegorz Cieslewski, Alan D. GeorgeOverhead and reliability analysis of algorithm-based fault tolerance in FPGA systems
                                                  12-57Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne LukParallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study
                                                  12-58Eric Matthews, Lesley Shannon, Alexandra FedorovaPolyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support
                                                  12-59Jaren Lamprecht, Brad L. HutchingsProfiling FPGA floor-planning effects on timing closure
                                                  12-60Jason Oberg, Ken Eguro, Ray Bittner, Alessandro ForinRandom decision tree body part recognition using FPGAs
                                                  12-61Chunmeng Bi, Tsutomu MaruyamaReal-time corner and polygon detection system on FPGA
                                                  12-62Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu AmanoReconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics
                                                  12-63Martin Kumm, Katharina Liebisch, Peter ZipfReduced complexity single and multiple constant multiplication in floating point precision
                                                  12-64Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip BriskRouting algorithms for FPGAS with sparse intra-cluster routing crossbars
                                                  12-65Yoshiaki Kono, Kentaro Sano, Satoru YamamotoScalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computation
                                                  12-66Florian Devic, Lionel Torres, Jérémie Crenne, Benoît Badrignans, Pascal Benoit: SecURe DPRSecure update preventing replay attacks for dynamic partial reconfiguration
                                                  12-67Jaime Espinosa, David de Andrés, Juan Carlos Ruiz, Pedro J. GilTolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments
                                                  12-68Carl Ingemarsson, Petter Kallstrom, Oscar GustafssonUsing DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs
                                                  12-69Doris Chen, Deshanand P. SinghUsing OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering
                                                  12-70Tim Todman, Wayne LukVerification of streaming designs by combining symbolic simulation and equivalence checking

                                                • eecejk
                                                  2013 paper list 13-1 Zsolt István, Gustavo Alonso, Michaela Blott, Kees Vissers A Flexible Hash Table Design for 10GBPs Key-Value Stores in FPGAs 13-2
                                                  Message 24 of 26 , Feb 9, 2015
                                                    2013 paper list

                                                    13-1Zsolt István, Gustavo Alonso, Michaela Blott, Kees Vissers A Flexible Hash Table Design for 10GBPs Key-Value Stores in FPGAs 
                                                    13-2David B. Thomas, Hideharu Amano A Fully Pipelined FPGA Architecture for Stochastic Simulation of Chemical Systems
                                                    13-3Dajung Lee, Pingfan Meng, Matthew Jacobsen, Henry Tse, Dino Di Carlo, Ryan Kastner A Hardware Accelerated Approach for Imaging Flow Cytometry 
                                                    13-4Davor Capalija, Tarek Abdelrahman A High-Performance Overlay Architecture for Pipelined Execution of Data Flow Graphs
                                                    13-5Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura A Packet Classifier Using LUT Cascades Based on EVMDDs(k) 
                                                    13-6Ricardo Ferreira, Luciana Rocha, Andre G. dos Santos, Jose A. Nacif, Stephan Wong, Luigi Carro A Run-Time Graph-Based Polynomial Placement and Routing Algorithm for Virtual FPGAs
                                                    13-7Arvind Arasu, Ken Eguro, Raghav Kaushik, Donald Kossmann, Ravi Ramamurthy, Ramaratnam Venkatesan A Secure Coprocessor for Database Applications 
                                                    13-8Gabriel Nazar, Leonardo P. Santos, Luigi Carro Accelerated FPGA Repair through Shifted Scrubbing 
                                                    13-9Ce Guo, Wayne Luk Accelerating Maximum Likelihood Estimation for Hawkes Point Processes 
                                                    13-10Chuan Cheng, Christos- Savvas Bouganis Accelerating Random Forest Training Process Using FPGA 
                                                    13-11Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Xiaomeng Huang, Youhui Zhang, Guangwen Yang Accelerating Solvers for Global Atmospheric Equations Through Mixed- Precision Data Flow Engine
                                                    13-12Parthasarathy Murali Baskar Rao, Abdulazim Amouri, Saman Kiamehr, Mehdi Tahoori Altering LUT Configuration for Wear-Out Mitigation of FPGA-Mapped Designs 
                                                    13-13Dirk Koch, Christian Beckhoff, Guy G.F. Lemieux An Efficient FPGA Overlay for Portable Custom Instruction Set Extensions 
                                                    13-14Dustin Richmond, Ryan Kastner, Ali Irturk, John McGarry An FPGA Design for High Speed Feature Extraction from a Compressed Measurement Stream
                                                    13-15Miguel Morales-Sandoval, Arturo Díaz-Pérez Area/Performance Evaluation of Digit-Digit GF(2^k) Multipliers on FPGAs 
                                                    13-16Nicolas Brunie, Florent de Dinechin, Kinga Illyes, Matei Istoan, Bogdan Popa Arithmetic Core Generation Using Bit Heaps 
                                                    13-17Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo Automated Synthesis of FPGA-Based Heterogeneous Interconnect Topologies 
                                                    13-18Safeen Huda, Jason Anderson, Hirotaka Tamura Charge Recycling for Power Reduction in FPGA Interconnect 
                                                    13-19Wei Ting Loke, Wenfeng Zhao, Yajun Ha Criticality-Based Routing for FPGAs with Reverse Body Bias Switch Box Architectures
                                                    13-20Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi Defect-Robust FPGA Architectures for Intellectual Property Cores in System LSI 
                                                    13-21Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo Dynamic Branch Prediction for High-Level Synthesis 
                                                    13-22Martin Langhammer, Bogdan Pasca Efficient Floating-Point Polynomial Evaluation on FPGAs 
                                                    13-23Karel Heyse, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt Efficient Implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAs
                                                    13-24Ren Chen, Hoang Le, Viktor K. Prasanna Energy Efficient Parameterized FFT Architecture 
                                                    13-25Panos Papantonakis, Charalampos Manifavas, Dionisios Pnevmatikatos, Ioannis Papaefstathiou Fast, FPGA-Based Rainbow Table Creation for Attacking Encrypted Mobile Communications
                                                    13-26Yi Wang, Yajun Ha FPGA Based ReKeying for Cryptographic Key Management in Storage Area Network
                                                    13-27Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado FPGA Implementation of Hierarchical Enumerative Coding for Locally Stationary Image Source
                                                    13-28Felix Winterstein, Samuel Bayliss, George A. Constantinides FPGA-Based K-Means Clustering Using Tree-Based Data Structures 
                                                    13-29Myron King, Asif Khan, Abhinav Agarwal, Oriol Arcas, Arvind Generating Infrastructure for FPGA-Accelerated Applications 
                                                    13-30Kubilay Atasu, Raphael Polig, Christoph Hagleitner, Frederick. R. Reiss Hardware-Accelerated Regular Expression Matching for High-Throughput Text Analytics
                                                    13-31Hongbin Zheng, Swathi Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow High-Level Synthesis with Behavioral Level Multi-Cycle Path Analysis 
                                                    13-32Chris Lavin, Brent Nelson, Brad Hutchings Impact of Hard Macro Size on FPGA Clock Rate and Place/Route Time 
                                                    13-33Anup Das, Shyamsundar Venkataraman, Akash Kumar Improving Autonomous Soft-Error Tolerance of FPGA Through LUT Configuration Bit Manipulation
                                                    13-34Andrew Love, Wenwei Zha, Peter Athanas In Pursuit of Instant Gratification for FPGA Design 
                                                    13-35Fredrik Brosser, Hui Yan Cheah, Suhaib Fahmy Iterative Floating Point Computation Using FPGA DSP Blocks 
                                                    13-36Di Wu, Kaveh Aasaraai, Andreas Moshovos Low-Cost, High-Performance Branch Predictors for Soft Processors 
                                                    13-37Matthew Naylor, Paul J. Fox, A. Theodore Markettos, Simon W. Moore Managing the FPGA Memory Wall: Custom Computing or Vector Processing? 
                                                    13-38Jiří Matoušek, Martin Skačan, Jan Kořenek Memory Efficient IP Lookup in 100 Gbps Networks 
                                                    13-39Martin Kumm, Martin Hardieck, Jens Willkomm, Peter Zipf, Uwe Meyer-Baese Multiple Constant Multiplication with Ternary Adders 
                                                    13-40Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel Emer Optimizing Under Abstraction: Using Prefetching to Improve FPGA Performance
                                                    13-41Sebastian Manz, Jano Gebelein, Andrei Oancea, Heiko Engel, Udo Kebschull Radiation Mitigation Efficiency of Scrubbing on the FPGA Based CBM-ToF Read- Out Controller
                                                    13-42Travis Haroldsen, Brent Nelson, Brad White Rapid FPGA Design Prototyping Through Preservation of System Logic: A Case Study
                                                    13-43Matthew Jacobsen, Ryan Kastner RIFFA 2.0: A Reusable Integration Framework for FPGA Accelerators 
                                                    13-44Giovanni Mariani, Vlad-Mihai Sima, Gianluca Palermo, Vittorio Zaccaria, Giacomo Marchiori, Cristina Silvano, Koen Bertels Run-Time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction
                                                    13-45José Leitão, José Germano, Nuno Roma, Ricardo Chaves, Pedro Tomás Scalable and High Throughput Biosensing Platform 
                                                    13-46Charles Chiasson, Vaughn Betz Should FPGAs Abandon the Pass-Gate? 
                                                    13-47Ruediger Willenberg, Paul Chow Simulation-Based HW/SW Co-Debugging for Field-Programmable Systems-On- Chip
                                                    13-48Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt StaticRoute: A Novel Router for the Dynamic Partial Reconfiguration of FPGAs 
                                                    13-49Mohamed Abdelfattah, Vaughn Betz The Power of Communication: Energy-Efficient NoCs for FPGAs 
                                                    13-50Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz Titan: Enabling Large and Complex Benchmarks in Academic CAD 
                                                    13-51Raphael Polig, Kubilay Atasu, Christoph Hagleitner Token-Based Dictionary Pattern Matching for Text Analytics 
                                                    13-52Aaron Severance, Guy Lemieux TputCache: High-Frequency, Multi-Way Cache for High-Throughput FPGA Applications
                                                    13-53Michael Feilen, Andreas Iliopoulos, Michael Vonbun, Walter Stechele Weighted Partitioning of Sequential Processing Chains for Dynamically Reconfigurable FPGAs

                                                  • eecejk
                                                    2014 paper list 14-1 Hasan Azgin, Serkan Yaliman and Ilker Hamzaoglu A High Performance Alternating Projections Image Demosaicing Hardware 14-2 Lin Gan,
                                                    Message 25 of 26 , Feb 9, 2015
                                                      2014 paper list

                                                      14-1Hasan Azgin, Serkan Yaliman and Ilker Hamzaoglu A High Performance Alternating Projections Image Demosaicing Hardware 
                                                      14-2Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Oskar Mencer, Xiaomeng Huang and Guangwen Yang A Highly-efficient and Green Data Flow Engine for Solving Euler Atmospheric Equations 
                                                      14-3Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi A Logic Cell Architecture Exploiting the Shannon Expansion for the Reduction of Configuration Memory
                                                      14-4Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol A Novel Modular Adder for One Thousand Bits and More Using Fast Carry Chains of Modern FPGAs 
                                                      14-5Jason Cong, Muhuan Huang and Kevin Lim A Scalable, High-Performance Customized Priority Queue 
                                                      14-6Christian Fobel, Gary Grewal and Deborah Stacey A Scalable, Serially-Equivalent, High-Quality Parallel Placement Methodology Suitable for Modern Multicore and GPU Architectures
                                                      14-7Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang and Colin Yu Lin A Semi-supervised Modeling Approach for Performance Characterization of FPGA Architectures 
                                                      14-8Yanbiao Li, Dafang Zhang, Xian Yu, Wei Liang, Jing Long and Hong Qiao Accelerate NDN Name Lookup using FPGA: Challenges and a Scalable Approach 
                                                      14-9James Davis and Peter Cheung Achieving Low-overhead Fault Tolerance for Parallel Accelerators with Dynamic Partial Reconfiguration
                                                      14-10Ghada Dessouky, Michael Klaiber and Sven Simon Adaptive Dynamic On-Chip Memory Management for FPGA-based Reconfigurable Architectures 
                                                      14-11Jian Gong, Tao Wang, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu and Jason Cong An Efficient and Flexible Host-FPGA PCIe Communication Library 
                                                      14-12Matthias Pohl, Michael Schäferling and Gundolf Kiefer An Efficient FPGA-based Hardware Framework for Natural Feature Extraction and Related Computer Vision Tasks
                                                      14-13Paul Grigoras, Gary Chow, Pavel Burovskiy and Wayne Luk An Efficient Sparse Conjugate Gradient Solver Using a Benes Permutation Network 
                                                      14-14Oriol Arcas-Abella, Geoffrey Ndu, Nehir Sonmez, Mohsen Ghasempour, Adria Armejach, Javier Navaridas, Wei Song, John Mawer, Adrian Cristal, Mikel Lujan An Empirical Evaluation of High-Level Synthesis Languages and Tools for Database Acceleration 
                                                      14-15Alexandru Amaricai, Constantina Elena Gavriliu and Oana Boncalo An FPGA Sliding Window-based Architecture Harris Corner Detector 
                                                      14-16Michael Kunz, Alexander Ostrowski and Peter Zipf An FPGA-optimized Architecture of Horn and Schunck Optical Flow Algorithm for Real-Time Applications
                                                      14-17Liucheng Guo, David Thomas, Ce Guo and Wayne Luk Automated Framework for FPGA-based Parallel Genetic Algorithms 
                                                      14-18Honlian Su, Yu Fujita and Hideharu Amano Body Bias Control for a Coarse Grained Reconfigurable Accelerator Implemented with Silicon on Thin BOX Technology
                                                      14-19Eric Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai and Masato Motomura Caching Memcached at Reconfigurable Network Interface 
                                                      14-20Soh Jun Jie and Nachiket Kapre Comparing Soft and Hard Vector Processing in FPGA-based Embedded Systems 
                                                      14-21Raphael Polig, Kubilay Atasu, Heiner Giefers and Laura Chiticariu Compiling Text Analytics Queries to FPGAs 
                                                      14-22Oana Boncalo, Alexandru Amaricai, Andrei Hera and Valentin Savin Cost Efficient FPGA Layered LDPC Decoder with Serial AP-LLR Processing 
                                                      14-23Rui Santos, Shyamsundar Venkataraman, Anup Das and Akash Kumar Criticality-aware Scrubbing Mechanism for SRAM-based FPGAs 
                                                      14-24Pavel Burovskiy, Stephen Girdlestone, Craig Davies, Spencer J Sherwin and Wayne Luk Dataflow Acceleration of Krylov Subspace Sparse Banded Problems 
                                                      14-25Kizheppatt Vipin and Suhaib A. Fahmy DyRACT: A Partial Reconfiguration Enabled Accelerator and Test Platform 
                                                      14-26Ernesto Sanchez, Luca Sterpone and Anees Ullah Effective emulation of permanent faults in ASICs through Dynamically Reconfigurable FPGAs 
                                                      14-27Jeffrey Goeders and Steve Wilton Effective FPGA Debug for High-Level Synthesis Generated Circuits 
                                                      14-28Stefan Wonneberger, Max Koehler, Wojciech Derendarz, Thorsten Graf and Rolf Ernst Efficient 3D Triangulation in Hardware for Dense Structure-from-Motion in Low-Speed Automotive Scenarios
                                                      14-29Andreas Becher, Florian Bauer, Daniel Ziener and Jürgen Teich Energy-aware SQL Query Acceleration through FPGA-based Dynamic Partial Reconfiguration 
                                                      14-30Roland Dobai Evolutionary On-line Synthesis of Hardware Accelerators for Software Modules in Reconfigurable Embedded Systems
                                                      14-31Fabio Garzia, Alexander Ruegamer, Robert Koch, Philipp Neumaier, Ekaterina Serezhkina, Matthias Overbeck and Guenther Rohmer Experimental Multi-FPGA GNSS Receiver Platform 
                                                      14-32Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang and Haigang Yang Exploring Architecture Parameters for Dual-Output LUT based FPGAs 
                                                      14-33Kenji Kanazawa and Tsutomu Maruyama FPGA Acceleration of SAT/Max-SAT Solving using Variable-way Cache 
                                                      14-34Youkou Sogabe and Tsutomu Maruyama FPGA Acceleration of Short Read Mapping Based on Sort and Parallel Comparison 
                                                      14-35Christophe Huriaux, Olivier Sentieys and Russell Tessier FPGA Architecture Support for Heterogeneous, Relocatable Partial Bitstreams 
                                                      14-36Zhenzhi Wu, Zheng Yang, Qingying Wang, Wie Zhou and Dake Liu FPGA Implementation of a Multi-Algorithm Parallel FEC for SDR Platforms 
                                                      14-37Junyi Liu, Helfried Peyrl, Andreas Burg and George Constantinides FPGA Implementation of an Interior Point Method for High-Speed Model Predictive Control 
                                                      14-38Pingfan Meng, Matthew Jacobsen, Motoki Kimura, Vladimir Dergachev, Thomas Anantharaman, Michael Requa and Ryan Kastner Hardware Accelerated Novel Optical De Novo Assembly for Large-Scale Genomes 
                                                      14-39Nithin George, Hyoukjoong Lee, David Novo, Tiark Rompf, Kevin Brown, Arvind Sujeeth, Martin Odersky Hardware System Synthesis from Domain-specific Languages 
                                                      14-40Siddhartha - and Nachiket Kapre Heterogeneous Dataflow Architectures for FPGA-based Sparse LU Factorization 
                                                      14-41Shane Fleming and David Thomas Heterogeneous Heartbeats: A Framework for the Dynamic Management of Autonomous SoCs 
                                                      14-42Dirk Koch and Christian Beckhoff Hierarchical Reconfiguration of FPGAs 
                                                      14-43Kenneth Zick, Sen Li and Matthew French High-Precision Self-Characterization for the LUT Burn-in Information Leakage Threat 
                                                      14-44Dajung Lee, Janarbek Matai and Ryan Kastner High-Throughput Channel Tracking for JTRS Wireless Channel Emulation 
                                                      14-45Abhinav Agarwal, Haitham Hassanieh, Omid Abari, Ezz Hamed, Dina Katabi and Arvind High-Throughput Implementation of a Million-Point Sparse Fourier Transform 
                                                      14-46Christian Brugger, Christian de Schryver and Norbert When HyPER: A Runtime Reconfigurable Architecture for Monte Carlo Option Pricing in the Heston Model 
                                                      14-47Farnaz Gharibian, Lesley Shannon and Peter Jamieson Identifying and Placing Heterogeneously-sized Cluster Groupings Based on FPGA Placement Data 
                                                      14-48Matthew Jacobsen, Siddarth Sampangi and Ryan Kastner Improving FPGA Accelerated Tracking with Multiple Online Trained Classifiers 
                                                      14-49A. Theodore Markettos, Paul J. Fox and Simon W. Moore Interconnect for Commodity FPGA Clusters: Standardized or Customized? 
                                                      14-50Bogdan Pasca Low-cost Multiplier Based FPU for Embedded Processing on FPGA 
                                                      14-51Mohamad Najem, Pascal Benoit, Florent Bruguier, Gilles Sassatelli and Lionel Torres Method for Dynamic Power Monitoring on FPGAs 
                                                      14-52Andrew Canis, Jason Helge Anderson and Stephen Dean Brown Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis 
                                                      14-53Shyamsundar Venkataraman, Rui Santos, Sidharth Maheshwari and Akash Kumar Multi-directional Error Correction Schemes for SRAM-based FPGAs 
                                                      14-54Joshua Monson and Brad Hutchings New Approaches for In-System Debug of Behaviorally-synthesized FPGA Circuits 
                                                      14-55Jinzhe Yang, Binghuan Lin, Wayne Luk and Terence Nahar Particle Filtering-based Maximum Likelihood Estimation for Financial Parameter Estimation 
                                                      14-56Wenlai Zhao, Haohuan Fu, Guangwen Yang and Wayne Luk Patra: Parallel Tree-reweighted Message Passing Architecture 
                                                      14-57Martin Kumm and Peter Zipf Pipelined Compressor Tree Optimization using Integer Linear Programming 
                                                      14-58Konrad Möller, Martin Kumm, Marco Kleinlein and Peter Zipf Pipelined Reconfigurable Multiplication with Constants on FPGAs 
                                                      14-59Christian Bechoff, Dirk Koch and Jim Torresen Portable Module Relocation and Bitstream Compression for Xilinx FPGAs 
                                                      14-60Umer Cheema, Gregory Nash, Rashid Ansari and Ashfaq Khokhar Power-efficient Re-gridding Architecture for Accelerating Non-uniform Fast Fourier Transform 
                                                      14-61Tuan D. A. Nguyen and Akash Kumar PR-HMPSoC: a Versatile Partially Reconfigurable Heterogeneous Multiprocessor System-on-Chip for Dynamic FPGA-based Embedded Systems
                                                      14-62Lei Xu, Hanyee Kim, Weidong Shi, Taeweon Suh and Xi Wang Privacy Preserving Large Scale DNA Readmapping in MapReduce Framework using FPGA 
                                                      14-63Khalid Javeed and Xiaojun Wang Radix-4 and Radix-8 Booth Encoded Interleaved Modular Multipliers Over General Fp 
                                                      14-64Fumito Yamaguchi, Kanae Matsui and Hiroaki Nishi RAM-based Hardware Accelerator for Network Data Anonymization 
                                                      14-65Teng Xu and Miodrag Potkonjak Robust and Flexible FPGA-based Digital PUF 
                                                      14-66Mohammad Hosseinabady and Jose Nunez-Yanez Run-Time Power Gating in Hybrid ARMFPGA Devices 
                                                      14-67Hirak Kashyap and Ricardo Chaves Secure Partial Dynamic Reconfiguration with Unsecured External Memory 
                                                      14-68Pablo Leyva, Gines Domenech-Asensi, Javier Garrigos, Julio Illade-Quinteiro, Victor Brea, Paula Lopez and Diego Cabello Simplification and Hardware Implementation of the Feature Descriptor Vector Calculation in the SIFT Algorithm
                                                      14-69Nazanin Calagar, Stephen Brown and Jason Anderson Source-Level Debugging for FPGA High-Level Synthesis 
                                                      14-70Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen, Fei Wang, Tongqiang Gao and Haigang Yang Survey of Open Source Processors for FPGAs 
                                                      14-71Kermin Fleming, Michael Adler, Hsin-Jung Yang and Joel Emer The LEAP FPGA Operating System 
                                                      14-72Tim Güneysu, Francesco Regazzoni, Marcin Wojcik and Pascal Sasdrich THOR - The Hardware Onion Router 
                                                      14-73Davor Capalija and Tarek Abdelrahman Tile-based Bottom-up Compilation of Custom Mesh-of-FUs FPGA Overlays 
                                                      14-74Ali Ahari, Hossein Asadi, Behnam Khaleghi, Zahra Ebrahimi and Mehdi Tahoori Towards Dark Silicon Era in FPGAs Using Complementary Hard Logic Design 
                                                      14-75Syed Mohammad Asad Hassan Jafri, Masoud Daneshtalab, Kolin Paul, Ahmed Hemani, Hannu Tenhunen, Guillerno Serreno and Naeem Abbas TransPar: Transformation Based Dynamic Parallelism for Low Power CGRAs 
                                                      14-76Eddie Hung, Tim Todman and Wayne Luk Transparent Insertion of Latency-oblivious Logic onto FPGAs 
                                                      14-77Mário Véstias and Horacio Neto Trends of CPU, GPU and FPGA for High-Performance Computing 
                                                      14-78Use Jasmina Vasiljevic and Paul Chow Using Buffer-to-BRAM Mapping Approaches to Trade-off Throughput vs. Memory 

                                                    • eecejk
                                                      2003 paper list 03-1 Barry Lee, Neil Burgess A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA 03-2 Yann Thoma, Eduardo Sanchez,
                                                      Message 26 of 26 , Feb 10, 2015
                                                        2003 paper list

                                                        03-1Barry Lee, Neil BurgessA Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA
                                                        03-2Yann Thoma, Eduardo Sanchez, Juan-Manuel Moreno Aróstegui, Gianluca TempestiA Dynamic Routing Algorithm for a Bio-inspired Reconfigurable Circuit
                                                        03-3Hideharu Amano, Akiya Jouraku, Kenichiro AnjoA Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device
                                                        03-4Martin Delvai, Ulrike Eisenmann, Wilfried ElmenreichA Generic Architecture for Integrated Smart Transducers
                                                        03-5Tomoyoshi Kobori, Tsutomu MaruyamaA High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA
                                                        03-6Jirong Liao, Weng-Fai Wong, Tulika MitraA Model for Hardware Realization of Kernel Loops
                                                        03-7J. Soares Augusto, Carlos Beltrán Almeida, H. C. Campos NetoA Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits
                                                        03-8Chang Hoon Kim, Soonhak Kwon, Jong Jin Kim, Chun Pyo HongA New Arithmetic Unit in GF(2m) for Reconfigurable Hardware Implementation
                                                        03-9Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier DemignyA Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring
                                                        03-10Maurizio Martina, Andrea Molino, Federico Quaglio, Fabrizio VaccaA Power-Scalable Motion Estimation Architecture for Energy Constrained Applications
                                                        03-11Yosuke Miyajima, Tsutomu MaruyamaA Real-Time Stereo Vision System with FPGA
                                                        03-12Toshihito Fujiwara, Kenji Fujimoto, Tsutomu MaruyamaA Real-Time Visualization System for PIV
                                                        03-13N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne LukA Reconfigurable Platform for Real-Time Embedded Video Image Processing
                                                        03-14Brandon Blodget, Philip James-Roxby, Eric Keller, Scott McMillan, Prasanna SundararajanA Self-reconfiguring Platform
                                                        03-15Chi Wai Yu, K. H. Kwong, Kin-Hong Lee, Philip Heng Wai LeongA Smith-Waterman Systolic Cell
                                                        03-16Theerayod Wiangtong, Peter Y. K. Cheung, Wayne LukA Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer
                                                        03-17Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy LauwereinsADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
                                                        03-18Sumit Mohanty, Viktor K. PrasannaAn Algorithm Designer's Workbench for Platform FPGA's
                                                        03-19John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, James Moscola, Sarang Dharmapurikar, David LimAn Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
                                                        03-20Stavros Paschalakis, Peter Lee, Miroslaw BoberAn FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors
                                                        03-21Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. StrolloAn FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm
                                                        03-22Leonel Sousa, Pedro Tomás, Francisco J. Pelayo, Antonio Martínez, Christian A. Morillas, Samuel F. RomeroAn FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time
                                                        03-23Allen Michalski, Kris Gaj, Tarek A. El-GhazawiAn Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers
                                                        03-24Georgi Kuzmanov, Stamatis VassiliadisArbitrating Instructions in an pmu-Coded CCM
                                                        03-25Henry Styles, Wayne LukBranch Optimisation Techniques for Hardware Compilation
                                                        03-26Gareth Lee, George MilneBuilding Run-Time Reconfigurable Systems from Tiles
                                                        03-27Tom Van Court, Martin C. Herbordt, Richard J. BartonCase Study of a Functional Genomics Application
                                                        03-28Lilian Bossuet, Guy Gogniat, Jean Luc PhilippeCommunication Costs Driven Design Space Exploration for Reconfigurable Architectures
                                                        03-29Elena Moscu Panainte, Koen Bertels, Stamatis VassiliadisCompiling for the Molen Programming Paradigm
                                                        03-30Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de AlegríaCore-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements
                                                        03-31Nuno Roma, Tiago Dias, Leonel SousaCustomisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs
                                                        03-32Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-ReilloData Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications
                                                        03-33Abdsamad Benkrid, Khaled Benkrid, Danny CrookesDesign and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs
                                                        03-34Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier LegatDesign Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES
                                                        03-35François Charot, Eslam Yahya, Charles WagnerEfficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA
                                                        03-36Matteo Sonza Reorda, Massimo ViolanteEmulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits
                                                        03-37Rohini Krishnan, José Pineda de Gyvez, Harry J. M. VeendrickEncoded-Low Swing Technique for Ultra Low Power Interconnect
                                                        03-38Andrzej KrasniewskiEvaluation of Testability of Path Delay Faults for User-Configured Programmable Devices
                                                        03-39Irwin KennedyExploiting Redundancy to Speedup Reconfiguration of an FPGA
                                                        03-40Herman SchmitExtra-dimensional Island-Style FPGAs
                                                        03-41Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. PopoviciFast Modular Division for Application in ECC on Reconfigurable Logic
                                                        03-42Ioannis Sourdis, Dionisios N. PnevmatikatosFast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System
                                                        03-43Abilio Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de SousaFault Simulation Using Partially Reconfigurable Hardware
                                                        03-44Rainer Feldmann, Christian Haubelt, Burkhard Monien, Jürgen TeichFault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques
                                                        03-45Jean-Luc BeuchatFPGA Implementations of the RC6 Block Cipher
                                                        03-46Linda Kaouane, Mohamed Akil, Yves Sorel, Thierry GrandpierreFrom Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations
                                                        03-47Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco Ballester, Francisco Mora CamposFully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA
                                                        03-48Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Robert W. Heikaus, Okan Erdogan, Peter F. Curran, Bryan S. Goda, Kuan Zhou, John F. McDonaldGigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory
                                                        03-49Jorge Barreiros, Ernesto CostaGlobal Routing for Lookup-Table Based FPGAs Using Genetic Algorithms
                                                        03-50Andrew Royal, Peter Y. K. CheungGlobally Asynchronous Locally Synchronous FPGA Architectures
                                                        03-51Roland H. C. Yap, Stella Z. Q. Wang, Martin HenzHardware Implementations of Real-Time Reconfigurable WSAT Variants
                                                        03-52Aneesh Koorapaty, Lawrence T. Pileggi, Herman SchmitHeterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics
                                                        03-53Christoph Steiger, Herbert Walder, Marco PlatznerHeuristics for Onine Scheduling Real-Time Tasks to Partially Reconfigurable Devices
                                                        03-54Thomas J. Wollinger, Christof PaarHow Secure Are FPGAs in Cryptographic Applications?
                                                        03-55M. Çakir, Eike Grimpe, Wolfgang NebelHW-Driven Emulation with Automatic Interface Generation
                                                        03-56Shih-Lien Lu, Konrad LaiImplementation of HW$im - A Real-Time Configurable Cache Simulator
                                                        03-57Yasunori Osana, Tomonori Fukushima, Hideharu AmanoImplementation of ReCSiP: A ReConfigurable Cell SImulation Platform
                                                        03-58Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui LiuImplementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
                                                        03-59John Oliver, Venkatesh AkellaImproving DSP Performance with a Small Amount of Field Programmable Logic
                                                        03-60Eryk Laskowski, Marek TudrujInter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches
                                                        03-61Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris GajIPsec-Protected Transport of HDTV over IP
                                                        03-62T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker DulayIrregular Reconfigurable CAM Structures for Firewall Applications
                                                        03-63Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed F. DeprettereLaura: Leiden Architecture Research and Exploration Tool
                                                        03-64Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk CorporaalLow Power Coarse-Grained Reconfigurable Instruction Set Processor
                                                        03-65Théodore Marescaux, Jean-Yves Mignolet, Andrei Bartic, W. Moffat, Diederik Verkest, Serge Vernalde, Rudy LauwereinsNetworks on Chip as Hardware Components of an OS for Reconfigurable Systems
                                                        03-66Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. CheungNon-uniform Segmentation for Hardware Function Evaluation
                                                        03-67Joaquín Cerdá, Rafael Gadea Gironés, Vicente Herrero, Angel SebastiaOn the Implementation of a Margolus Neighborhood Cellular Automata on FPGA
                                                        03-68K. R. Shesha Shayee, Joonseok Park, Pedro C. DinizPerformance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations
                                                        03-69François-Xavier Standaert, Loïc van Oldeneel tot Oldenzeel, David Samyde, Jean-Jacques QuisquaterPower Analysis of FPGAs: How Practical is the Attack?
                                                        03-70John Teifel, Rajit ManoharProgrammable Asynchronous Pipeline Arrays
                                                        03-71Ludovico de Souza, Philip J. Ryan, Jason Crawford, Kevin Wong, Gregory B. Zyner, Tom McDermottPrototyping for the Concurrent Development
                                                        03-72Sean T. McCulloch, James P. CohoonQuark Routing
                                                        03-73Steve Ferrera, Nicholas P. CarterReconfigurable Circuits Using Hybrid Hall Effect Devices
                                                        03-74Iouliia Skliarova, António de Brito FerrariReconfigurable Hardware SAT Solvers: A Survey of Systems
                                                        03-75Toshiro Kitaoka, Hideharu Amano, Kenichiro AnjoReducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device
                                                        03-76Klaus Danne, Christophe Bobda, Heiko KalteRun-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration
                                                        03-77Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky CatthoorRun-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems
                                                        03-78Eric Keller, Gordon J. Brebner, Philip James-RoxbySoftware Decelerators
                                                        03-79Seyed Ghassem Miremadi, Ali Reza EjlaliSwitch Level Fault Emulation
                                                        03-80Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-TerreSymbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S
                                                        03-81Jose Antonio Boluda, Fernando PardoSynthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System
                                                        03-82Paul Berube, Ashley Zinyk, José Nelson Amaral, Mike H. MacGregorThe Bank Nth Chance Replacement Policy for FPGA-Based CAMs
                                                        03-83Seonil Choi, Viktor K. PrasannaTime and Energy Efficient Matrix Factorization Using FPGAs
                                                        03-84Katherine Compton, Scott HauckTrack Placement: Orchestrating Routing Structures to Maximize Routability
                                                        03-85Nazar A. Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-PérezTwo Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
                                                        03-86Tony StansfieldUsing Multiplexers for Control and Data in D-Fabrix
                                                        03-87Ivan Gonzalez, Sergio López-Buedo, Francisco J. Gómez, Javier MartínezUsing Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm
                                                        03-88Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe CocorulloVariable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems
                                                        03-89Máire McLoone, John V. McCannyVery High Speed 17 Gbps SHACAL Encryption Architecture
                                                        03-90Rolf Enzler, Christian Plessl, Marco PlatznerVirtualizing Hardware with Multi-context Reconfigurable Arrays

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